Discrete Approach to PWL Analog Modeling in VHDL Environment

DabrowskiJerzy,; PułkaAndrzej,

doi:10.1007/978-1-4615-5753-1_2

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2000

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“…Digital parts are then modeled using a standard HDL. Instead, in order to model the analog parts with a digital HDL, the user must define a time domain function , which is a very time consuming task [2] . Besides, the resulting analog model cannot be directly compared to the transistor level description of the circuit using only a logic simulator.…”

Section: Introductionmentioning

confidence: 48%

RF Interface Design Using Mixed Mode Methodology

Gallegos

Silvestre

Robert

et al. 2000

VLSI: Systems on a Chip

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Abstract:A VHDL-SPICE mixed-signal modeling methodology is applied to the RF interface of a DECT ASIC designed in CMOS 0.35 f.lm technology. An overview of actual mixed design flows is presented followed by the DECT system description. Then a mixed-signal methodology is introduced to validate the whole circuit behavior. We illustrate the approach with detailed models, simulation results and experimental data. The chip was successfully tested and produced by VLSI Technology.

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Section: Introductionmentioning

confidence: 48%