Dislocation propagation and emitter edge defects in silicon wafers

Abstract

Some transistor defects show a tendency to occur near the edges of emitters. Like ’’area defects’’, these ’’edge defects’’ occur in silicon wafers in a distribution pattern reminiscent of thermal-stress-induced dislocations. A peculiar feature is that often a number of edge defects which are close replicas of one another occur in a string, each in one of the neighboring emitters. Such edge defects are preponderant in transistors having silicon nitride surface films. In our proposed model, these emitter edge defects are generated when thermal-stress-induced dislocations glide through a row of emitters and interact with the emitter edge stresses, thereby, and under appropriate conditions, casting off small dislocation half-loops which straddle the edges. The model is shown to be consistent with all the observed phenomena pertaining to the emitter edge defect. To provide a foundation for the discussion of the finer details of the emitter edge defects, we also present an analysis of the nature and distribution of thermally induced dislocations, itself a topic of general interest.

Depth distribution of plasma induced damage and dislocation generation due to an interaction of subsequent oxidation

“…This technique is effective to evaluate the RIE induced damage. [11][12][13] These results indicated that an interaction of RIE damage and subsequent oxidation can form lattice defects even though RIE damage was decreased to suppress OSF generation. The results for existence of defects are summarized in Table I.…”

“…Reverse bias current characteristics of the n ϩ -p junctions of both the RIE induced sample and the control one fabricated by the ULSI field isolation process are shown in Fig. 11,13 Accordingly, it seems that this carbon contained amorphous layer near the film edge becomes a trigger to the generation of dislocations, while oxidation proceeds. The control structure was fabricated with the SiN/SiO 2 RIE process that the etching was stopped on the SiO 2 not to induce damage.…”

X-ray diffractometry and topography of lattice plane curvature in thermally deformed Si wafer

“…Saddle-type warpage, which was observed by a standard flatness tester, was generated owing to the radial stress induced by the thermal gradient. Line patterns (surface features of slip bands) appeared at the wafer edges of the /8 and h110i zones with 45 periodicity (Hu et al, 1976), extending into the center along the h110i direction with length 25-30 mm. The slip bands were observed as a pair with a separation distance of about 1 mm, as confirmed by optical microscope (inset of Fig.…”

“…Wafer warpage owing to thermal stress in a very large scale integrated-circuit fabrication is a rediscovered issue of concern at each step of Si wafer enlargement (Hu, 1973;Leroy & Plougonven, 1980;Widmer & Rehwald, 1986;Sueoka et al, 1997;Fischer et al, 2000). Extensive efforts have been devoted to elucidate the onset mechanism of wafer warpage with an emphasis on the distribution of thermal stress within a wafer (Hu et al, 1976;Bentini et al, 1984) and/or on the effect of oxygen precipitates that are incorporated by the precipitation treatments (Leroy & Plougonven, 1980;Fukuda & Moizuka, 1992;Chiou et al, 1994). The experimental and theoretical results have shown that the macroscopic shape, saddle or cuptype in thermally warped Si wafers depends on the tensile or compressive stress during thermal treatments.…”

Slip-free processing of 300 mm silicon batch wafers

“…Once the temperature distribution is calculated, the distribution of stress and r can be found easily for axially symmetric plane stress problems. 8,11,12 Because of axisymmetry, the shear component r is zero. Then, the maximum resolved shear stress T that acts on the slip systems ͕111͖͗110͘ in ͕100͖ silicon wafers having radial temperature gradients is given by 11…”