During evaluation of negative bias temperature instability (NBTI) in short-channel devices, we found that using an optimized nitrogen depth profile is important in suppressing NBTI when scaling down CMOS devices. Performing the NO anneal process before oxidation yeilds good transistor performance, suppressing NBTI by 25%. When using more nitrogen to moderate gate leakage and boron penetration, in addition to the amount of nitrogen, it is important to control the depth profile of the nitrogen on gate insulator, as our research shows that the interface peak concentration of nitrogen enhances NBTI degradation.Index Terms-Gate insulator, MOSFET, negative bias temperature instability (NBTI), nitrogen depth profile, NO annealing, SiO2.

We investigated HfO2 etching characteristics in conventional Si gate etching chemistries, namely, CF4 and Cl2/HBr/O2-based chemistries. We obtained an adequate etch rate of 2.0 nm/min for both chemistries and a selectivity of 1.9 over SiO2 for Cl2/HBr/O2-based chemistry. We examined the etch rate dependence on source power, bias power, O2 flow rate, and Cl2 flow rate in the Cl2/HBr/O2 chemistry. It was clarified that a physical component is dominant in HfO2 etching in this chemistry. The possibilities of achieving a higher HfO2/SiO2 selectivity and of controlling the anisotropic/isotropic component in HfO2 patterning were also discussed. Moreover, it was clarified that the surface portion of the damaged layer created by the dry-etching step can be removed by a subsequent wet etching. Based on these results, the sub-100 nm patterning of poly-Si/HfO2 gate stacks was successfully demonstrated.

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In this paper, the effects of boron and fluorine in the SiO2/Si interface region with the optimized nitrogen profile are described. Fluorine in the interface region has been found to terminate the interface states and improve negative bias temperature instability (NBTI). However, fluorine enhances the boron penetration. The ideal nitrogen profile has been achieved in order to suppress NBTI characteristics by applying the SiN/SiO2 stack structure.

stacks causes the charge trapping by BTI. Fig. 5(a) and 5@) show This paper describes the SiN-capped HfSiON gate stacks for the device lifetime under negative bias temperature (NBT) stress 65 nn-node low-standby-power transistors with improved bias for pEFTs, and positive bias temperahue (PBT) stress for nFETs, temperature instabilities (BTI). By employing SiN-cap on respectively. The stress temperature is 125T. The thicker SiN HfSiON and the counter-implant for adjustment of pFET's (20-cycles) samples show poorer immunities against both NBT threshold voltage (Vm), the symmetrical V, values for nFETs and PBT stress than the thinner SiN (lo-cycles) samples. It should and pFETs havc been obtained. The nitrogen incorporation in the be noted that the lifetime under PBT stress is much smaller than interfacial oxide prevents the interface states generation under that under NBT stress. The slopes of the dependence of lifetime .positive bias temperature stress. Negative BTI can he improved by on IN, are different for PBT and NBT stress. Furthermore, the reducing the thickness of SiN-cap. 10-year lifetimes for both lifetimes of the samples treated by NH3 at 600 and 700'C are positive and negative BTI have been achieved.reversed. These results suggest that the degradation mechanisms Keywords: high-k, HfSiON, SiN-cap and Bias temperahue under NBT and PBT stress are different. Fig. 6(a) and @) show the increase in charge pumping current (I,) after IO4 sec NBT