SiN-capped HfSiON gate stacks with improved bias temperature instabilities for 65 nm-node low-standby-power transistors

Tamura, Y.; Sasaki, Takaoki; Izumi, Naoki; Ootsuka, F.; Yasuhira, M.; Hoshi, Takeshi; Kume, Shouji; Amai, H.; Ida, Takashi; Aoyama, T.; Kamiyama, Satoshi; Torii, Kazuyoshi; Kitajima, Hiroshi; Arikado, T.

doi:10.1109/vlsit.2004.1345484

Cited by 7 publications

(5 citation statements)

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“…15,16 In this transistor device fabrication process, counterimplantation was applied to reduce the V FB /Vth for p-MOSFETs after the well formation. 21 The channel doping concentrations were about 5 and 3 ϫ 10 17 cm −3 for n-MOS and p-MOSFETs, respectively. After the formation of high-k gate stack dielectrics, the films were nitrided using a nitrogen radical plasma treatment.…”

Section: Methodsmentioning

confidence: 99%

Comparison of the Electrical Properties of Poly-Si/Hf-Silicate Gate Stacks Fabricated by ALD Employing BDMAS and TDMAS Precursors

Kamiyama¹,

Miura²,

Nara³

2006

J. Electrochem. Soc.

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We studied the electrical properties of polysilicon/hafnium ͑Hf͒-silicate gate stacks with various controlled Hf/͑Hf + Si͒ compositions, using bis-dimethylamino-silane ͑BDMAS: SiH 2 ͓N͑CH 3 ͒ 2 ͔ 2 ͒ and tris-dimethylamino-silane ͑TDMAS: SiH͓N͑CH 3 ͒ 2 ͔ 3 ͒ as precursors. The high-k films were fabricated by atomic layer deposition ͑ALD͒ using Hf͓N͑CH 3 ͒͑C 2 H 5 ͔͒ 4 and each of the Si precursors in turn. O 3 was used as an oxidant. Effective oxide thicknesses ͑EOTs͒ were reduced in line with increasing Hf contents: the very thin dielectric ͑EOT = 1.18 nm͒ was fabricated with a Hf/͑Hf + Si͒ composition of 74%. The flatband voltage ͑V FB ͒ shift of p-type metal oxide semiconductor field effect transistors ͑p-MOSFETs͒ employing either Si precursor were improved by reducing the Hf/͑Hf + Si͒ composition: the value of V FB shift was improved to about 0.25-0.26 V for Hf-silicate gate stacks in which Hf/͑Hf + Si͒ composition was reduced from 72-74% to 21-23%. The subthreshold swings ͑S values͒ were dependent on the Hf content in the p-MOSFETs employing both Si precursors. By using the gate length ͑Lg͒ of the transistors as 75 nm, S values varied from 92 to 105 mV/dec for Hf/͑Hf + Si͒ composition ratios from 21 to 74%, respectively, due to a Fermi-level pinning problem. Inspection of subthreshold characteristics of n-MOSFETs revealed values of I on at V dd = 1.1 V, which were greater than 350 A/m, while I off was less than 50 pA/m, using either Si precursor ͑Lg = 75 nm͒. With the p-MOSFETs, the values of I on at V dd = −1.1 V for Hf-silicate gate stacks in which Hf/͑Hf + Si͒ composition was between 21 and 23% were approximately 30-40 A/m greater than those in which Hf/͑Hf + Si͒ composition was between 72 and 74%. The leakage current densities were dependent on the Hf content in the Hf-silicate gate stacks. However, those were independent of the Si precursors for the Hf-silicate gate stacks with the same Hf content, because the carbon impurity concentrations near the surface of the annealed layers at 1000°C were about 1 ϫ 10 20 cm −3 for both Si precursors.For many years, silicon dioxide ͑SiO 2 ͒ films have been the gate dielectric in complementary metal oxide semiconductor ͑CMOS͒ devices. For gate oxide thicknesses of less than 3.5 nm, the direct tunneling current increases by a factor of 100 times for each 0.4-0.5 nm decrease in thickness. 1,2 This high gate leakage current increases the standby power consumption. 2 In order to reduce the leakage current due to direct tunneling, high-dielectric-constant ͑high-k͒ materials allow for an increase in the physical thickness while maintaining a low equivalent oxide thickness. 3-8 Among the many high-k materials available, those based on Hf and its nitride exhibit low leakage currents and high carrier mobility. 7,8 Sputtering and metallorganic chemical vapor deposition ͑MOCVD͒ are two methods that have been used for the formation of high-k films. 3-8 Another possible deposition technique is atomic layer deposition ͑ALD͒, which has some desirable features in that it allows pre...

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Section: Methodsmentioning

confidence: 99%

Comparison of the Electrical Properties of Poly-Si/Hf-Silicate Gate Stacks Fabricated by ALD Employing BDMAS and TDMAS Precursors

Kamiyama¹,

Miura²,

Nara³

2006

J. Electrochem. Soc.

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“…After the implantation and interfacial oxide formation, HfSiO was deposited by metal-organic chemical vapor deposition (MOCVD), followed by O 3 and NH 3 treatments at 700 C for nitridation in the same chamber. 4,8) The physical thicknesses of the final HfSiON and interfacial SiO 2 are 2.5 and 0.5 nm, respectively. An ultrathin SiN layer was deposited by cyclic CVD for 10 cycles as an option after the HfSiON deposition.…”

Section: Device Fabrication and Measurementsmentioning

confidence: 99%

“…The ultrathin SiN cap layer leads to the negative threshold voltage shift, especially for the PMOS, which can be attributed to the reduction in the degree of Fermi level pinning at the polySi/HfSiON interface. 8) During the bias temperature stress, the gate electrode was biased at a constant voltage and the other electrodes (source, drain, and well) were grounded. The temperature ranged from room temperature to 150 C with a stability of AE1 C. The stress was interrupted regularly to measure I d -V g characteristics in a small V g range around V th to minimize the recovery effect.…”

Section: Device Fabrication and Measurementsmentioning

confidence: 99%

“…[2][3][4] However, the possible chemical reaction between the polycrystalline silicon (polySi) gate and the HfSiON dielectrics may lead to an undesirable threshold voltage (V th ) shift. 5) To circumvent this problem and improve the transistor performance, a cap layer insertion into HfSiON has recently been reported by using AlO x , 6) La 2 O 3 , 7) SiN, 8) or low-hafnium-concentration layer. 9) On the other hand, bias temperature instability (BTI) is one of the critical reliability issues for the modern complementary MOS (CMOS) technology.…”

Section: Introductionmentioning

confidence: 99%

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Effect of an Ultrathin SiN Cap Layer on the Bias Temperature Instability in Metal–Oxide–Semiconductor Field-Effect Transistors with HfSiON Gate Stacks

Zhu¹,

Takeue²,

Nakajima³

2010

Jpn. J. Appl. Phys.

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The negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) of HfSiON/SiO2 metal–oxide–semiconductor field-effect transistors (MOSFETs) with and without an ultrathin SiN cap layer were investigated. For the PBTI of n-channel MOSFETs, the dominant degradation mechanism is the electron tunneling from the Si channel and electron trapping in the pre-existing traps in HfSiON. The SiN cap layer does not make a significant difference in PBTI. For the NBTI of p-channel MOSFETs, on the other hand, both the electron trapping in HfSiON and the dissociation of Si–H bonds at the SiO2/channel-Si interface (i.e., the interface trap generation) play a role and the SiN cap layer makes a significant difference in NBTI: the dominant degradation mechanism for the devices without the SiN cap layer is the electron trapping in HfSiON, whereas that for the devices with the SiN cap layer is the interface trap generation. This indicates that the interfacial SiN cap layer can effectively suppress the electron tunneling from the polycrystalline silicon (polySi) gate to HfSiON under the NBT stress.

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“…The use of a high quality interfacial SiO 2 layer is also beneficial. Therefore, HfSiON is thought to be the most promising material for use at the hp65 node (1)(2)(3)(4). The application of this particular material to the further scaled devices, such as the hp45 node and beyond, is the most straightforward from the fabrication point of view.…”

Section: Introductionmentioning

confidence: 99%

HfSiON Gate Dielectrics for hp45 Node and Beyond

et al. 2006

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In order to fabricate sub-0.9nm EOT HfSiON gate dielectrics, we have investigated post-high-k-deposition processes. We found that plasma nitridation and post-nitridation annealing are the key processes for realizing low leakage currents and high carrier mobility with reduced EOT. By using low-pressure plasma nitridation and high temperature post-nitridation annealing, we have successfully fabricated a 0.81nm-EOT HfSiON gate dielectric with a gate leakage current of 0.74A/cm 2 at 0.7V and an electron mobility of 235cm 2 /Vs at 0.8MV/cm, which can be applied to low operating power devices at the hp45 and hp32 technology nodes.

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SiN-capped HfSiON gate stacks with improved bias temperature instabilities for 65 nm-node low-standby-power transistors

Cited by 7 publications

References 0 publications

Comparison of the Electrical Properties of Poly-Si/Hf-Silicate Gate Stacks Fabricated by ALD Employing BDMAS and TDMAS Precursors

Comparison of the Electrical Properties of Poly-Si/Hf-Silicate Gate Stacks Fabricated by ALD Employing BDMAS and TDMAS Precursors

Effect of an Ultrathin SiN Cap Layer on the Bias Temperature Instability in Metal–Oxide–Semiconductor Field-Effect Transistors with HfSiON Gate Stacks

HfSiON Gate Dielectrics for hp45 Node and Beyond

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