Distributed matched bypassing for board-level power distribution networks

Novak, Istvan; Noujeim, L.M.; Cyr, V.S.; Biunno, N.; Patel, Amit; Korony, G.; Ritter, Andrew

doi:10.1109/tadvp.2002.803265

Cited by 33 publications

(21 citation statements)

References 12 publications

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“…As described in [14], the ESR of the decoupling capacitors does not change the location of the poles and zeros of the power distribution system impedance, only the damping factor of the RLC system formed by the decoupling capacitor is affected. Representing a decoupling capacitor with a series LC network, the impedance of the power distribution system with dual power supply voltages is (5) where…”

Section: A Impedance Of a Power Distribution Systemmentioning

confidence: 99%

Decoupling Capacitors for Multi-Voltage Power Distribution Systems

Jakushokas

Popovich

Mezhiba

et al. 2010

Power Distribution Networks With on-Chip Decoupling Capacitors

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Abstract-Multiple power supply voltages are often used in modern high-performance ICs, such as microprocessors, to decrease power consumption without affecting circuit speed. To maintain the impedance of a power distribution system below a specified level, multiple decoupling capacitors are placed at different levels of the power grid hierarchy. The system of decoupling capacitors used in power distribution systems with multiple power supplies is described in this paper. The noise at one power supply can propagate to the other power supply, causing power and signal integrity problems in the overall system. With the introduction of a second power supply, therefore, the interaction between the two power distribution networks should be considered.The dependence of the impedance and magnitude of the voltage transfer function on the parameters of the power distribution system is investigated. An antiresonance phenomenon is intuitively explained in this paper. It is shown that the magnitude of the voltage transfer function is strongly dependent on the parasitic inductance of the decoupling capacitors, decreasing with smaller inductance. Design techniques to cancel and shift antiresonant spikes out of range of the operating frequencies are presented. It is also shown that it is highly desirable to maintain the effective series inductance of the decoupling capacitors as low as possible to decrease the overshoots of the response of the dual-voltage power distribution system over a wide range of operating frequencies. A criterion for an overshoot-free voltage response is presented in this paper. It is noted that the frequency range of the overshoot-free voltage response can be traded off with the magnitude of the response.

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Section: A Impedance Of a Power Distribution Systemmentioning

confidence: 99%

Decoupling Capacitors for Multi-Voltage Power Distribution Systems

Jakushokas

Popovich

Mezhiba

et al. 2010

Power Distribution Networks With on-Chip Decoupling Capacitors

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“…Most available decoupling capacitors, however, have moderate or high quality factor (Q), making it a challenge to create the flat impedance profile required. It has been shown ( [6], [7]) that bypass capacitors with help to create flat impedance profiles with a minimum number of components. For fixed equivalent series resistance (ESR) and equivalent series inductance (ESL), the Q of the capacitor varies inversely with capacitance.…”

Section: B Bypass Capacitorsmentioning

confidence: 99%

“…Providing a smooth impedance profile with multiple lower-valued low-ESR ceramic capacitors is difficult and challenging, especially when the frequency dependency of capacitance, resistance and inductance are taken into account. In [6] the bypass quality factor (BQF) was introduced as a measure of effectiveness of the capacitor to cover a wide frequency range where (C: Capacitance; L: Inductance), indicating that a capacitor is more effective if the C/L ratio is higher. For several hundred microfarad and higher capacitance values tantalum, niobium and various electrolytic capacitors have been used.…”

Section: B Bypass Capacitorsmentioning

confidence: 99%

Power distribution networks for system-on-package: status and challenges

Swaminathan

Kim

Novak

et al. 2004

IEEE Trans. Adv. Packag.

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232

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Abstract-The power consumption of microprocessors isincreasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product generation. In the last decade, high I/O ball grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.

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“…A successful PDN design requires the power/ground loops presenting acceptable impedances at all frequencies of interest. Many previous works focused on the worst voltage drop in time- [6], [7], [8] and in frequency-domain [9], [10], [11] Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored.…”

Section: Introductionmentioning

confidence: 99%

Worst-Case Noise Area Prediction of On-Chip Power Distribution Network

Zhang¹,

Liu

et al. 2014

Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop

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Abstract-We propose a prediction of the worst-case noise area of the supply voltage on the power distribution network (PDN). Previous works focus on the worst-peak droop to sign off PDN. In this work, we (1) study the behavior of circuit delay over the worst-area noise (2) study the worst-case noise area of a lumped PDN model (3) develop an algorithm to generate the worst-case current for general PDN cases (4) predict the longest delay of a datapath due to power integrity. Experimental results show that the worst-area noise induces additional delay than that of the worst-peak noise.

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Distributed matched bypassing for board-level power distribution networks

Cited by 33 publications

References 12 publications

Decoupling Capacitors for Multi-Voltage Power Distribution Systems

Decoupling Capacitors for Multi-Voltage Power Distribution Systems

Power distribution networks for system-on-package: status and challenges

Worst-Case Noise Area Prediction of On-Chip Power Distribution Network

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