Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop 2014
DOI: 10.1145/2633948.2633950
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Worst-Case Noise Area Prediction of On-Chip Power Distribution Network

Abstract: Abstract-We propose a prediction of the worst-case noise area of the supply voltage on the power distribution network (PDN). Previous works focus on the worst-peak droop to sign off PDN. In this work, we (1) study the behavior of circuit delay over the worst-area noise (2) study the worst-case noise area of a lumped PDN model (3) develop an algorithm to generate the worst-case current for general PDN cases (4) predict the longest delay of a datapath due to power integrity. Experimental results show that the wo… Show more

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Cited by 2 publications
(1 citation statement)
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“…Placement remains dominant on the overall quality of physical design automation [29,30]. Based on logic synthesis [31], back-end design on timing [45], power [9,44], routability [8,38], variability [3,42] etc. are highly impacted by placement performance.…”
Section: Introductionmentioning
confidence: 99%
“…Placement remains dominant on the overall quality of physical design automation [29,30]. Based on logic synthesis [31], back-end design on timing [45], power [9,44], routability [8,38], variability [3,42] etc. are highly impacted by placement performance.…”
Section: Introductionmentioning
confidence: 99%