ePlace-3D

Lu, Jingwei; Zhuang, Hao; Kang, Ilgweon; Chen, Pengwen; Cheng, Chung‐Kuan

doi:10.1145/2872334.2872361

Cited by 36 publications

(2 citation statements)

References 43 publications

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“…Moreover, proposed a novel relaxed conflict-net (RCN) graph based layer assignment method to refine the 3D placements 14 . Uses an electrostatics based 3D density function ensuring global smoothness with 3D numerical solution based on fast Fourier transform (FFT) and improved spectral formulation 12 . A nonlinear 3D pre-conditioner is introduced in 12 to equalise all the moving objects in the optimisation perspective and to enhance efficiency, interleaving coarse-grained 3D placement with fine grained 2D placement is used.…”

Section: Related Work and Motivational Backgroundmentioning

confidence: 99%

“…Currently, two type of 3D-IC placement techniques are popular, namely, folding based and partitioning based methods. Folding based method 6 use the 2D-IC placement layout and produce 3D layout by folding with local refinement and Partitioning based approaches [7][8][9][10][11][12] by minimising the usage of TSVs. Although, these tools are succeeded in 3D placement, still suffer from initial overlaps on the layer and complex partitioning for the TSVs resulting in increased design time and a large TSV count.…”

Section: Introductionmentioning

confidence: 99%

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Fast 3D Integrated Circuit Placement Methodology using Merging Technique

et al. 2019

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In the recent years the advancement in the field of microelectronics integrated circuit (IC) design technologies proved to be a boon for design and development of various advanced systems in-terms of its reduction in form factor, low power, high speed and with increased capacity to incorporate more designs. These systems provide phenomenal advantage for armoured fighting vehicle (AFV) design to develop miniaturised low power, high performance sub-systems. One such emerging high-end technology to be used to develop systems with high capabilities for AFVs is discussed in this paper. Three dimensional IC design is one of the emerging field used to develop high density heterogeneous systems in a reduced form factor. A novel grouping based partitioning and merge based placement (GPMP) methodology for 3D ICs to reduce through silicon vias (TSVs) count and placement time is proposed. Unlike state-of-the-art techniques, the proposed methodology does not suffer from initial overlap of cells during intra-layer placement which reduces the placement time. Connectivity based grouping and partitioning ensures less number of TSVs and merge based placement further reduces intra layer wire-length. The proposed GPMP methodology has been extensively against the IBMPLACE database and performance has been compared with the latest techniques resulting in 12 per cent improvement in wire-length, 13 per cent reduction in TSV and 1.1x improvement in placement time.

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Section: Related Work and Motivational Backgroundmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Fast 3D Integrated Circuit Placement Methodology using Merging Technique

et al. 2019

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Deep Learning Based Placement Acceleration for 3D-ICs

Cheng

Zhang

et al. 2021

Communications in Computer and Information Science

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A graph placement methodology for fast chip design

Mirhoseini

Goldie

Yazgan

et al. 2021

Nature

404

144

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In physical design, human designers typically place macros via trial and error, which is a Markov decision process. Reinforcement learning (RL) methods have demonstrated superhuman performance on the macro placement. In this paper, we propose an extension to this prior work [1]. We first describe the details of the policy and value network architecture. We replace the force-directed method with DREAMPlace for placing standard cells in the RL environment. We also compare our improved method with other academic placers on public benchmarks.

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ePlace-3D

Cited by 36 publications

References 43 publications

Fast 3D Integrated Circuit Placement Methodology using Merging Technique

Fast 3D Integrated Circuit Placement Methodology using Merging Technique

Deep Learning Based Placement Acceleration for 3D-ICs

A graph placement methodology for fast chip design

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