Distributed-Memory-Based FFT Architecture and FPGA Implementations

Abstract

A new class of fast Fourier transform (FFT) architecture, based on the use of distributed memories, is proposed for field-programmable gate arrays (FPGAs). Prominent features are high clock speeds, programmability, reduced look-up-table (LUT) and register usage, simplicity of design, and a capability to do both power-of-two and non-power-of-two FFTs. Higher clock speeds are a consequence of new algorithms and a more fine-grained structure compared to traditional pipelined FFTs, so clock speeds are typically >500 MHz in 65 nm FPGA technology. The programmability derives from the memory-based architecture, which is also scalable. Reduced LUT and register usage arises from a unique methodology to control word growth during computation that achieves high dynamic range, along with inherent systolic circuit characteristics: simple, regular, uniform arrays of processing elements, connected in nearest-neighbor fashion to minimize wiring lengths. The circuit goal was to maximize throughput and minimize the use of the FPGA LUT and register logic fabric. Comparison results from seven different designs, covering a spectrum of functionality (fixed-size, variable, floating-point and variable non-power-of-two FFTs), different FPGA vendors (Intel and Xilinx) and different FPGA types, showed increases in throughput per logic cell up to 181% with an average improvement of 94%.

HC-FFT: highly configurable and efficient FFT implementation on FPGA

“…the deviation divided by the Xilinx IP's output) was less than 0.00001 in all configurations. [13,27,32] as well as the Xilinx IP.…”

“…HC-FFT processes 4-parallel samples in each cycle, however, Xilinx FFT IP processes 1 sample per cycle. [27] compared to our proposed design. Some parts of the utilization components are not reported in [32].…”

“…Now, we will go over the works in Table 1 one by one. In [27], radix-4 MDC decimation in frequency (DIF) parallel pipeline FFT processor is presented for a very high-speed orthogonal frequency-division multiplexing (OFDM) communication systems. Such FFT processor supports the computation of one stream of variable-length FFT with 16, 64, 256, and 1024 pts.…”

Using the complement of the cosine to compute trigonometric functions

“…The latter definition is relevant since, in many applications, the constant angle φ is trigonometric binary. For example, consider the algorithms designed to compute efficiently the DFT called fast Fourier transform (FFT) [12] algorithms: many of these algorithms require the length of the transform L to be a power of 2 [13], that is, log 2 (L) must be an integer, and hence φ must be trigonometric binary since H t (φ) = log 2 (λ t (−2π/L)) = log 2 (L). Moreover, in applications where φ is trigonometric binary, it is irrelevant whether the representation of n is either unsigned or two's complement as long as w ≥ H t (φ).…”

Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs

“…The applications of FPGAs are constantly increasing, specifically, in the field of networking, security, and artificial intelligence [1,19,20], but modern FPGAs lack a soft core for CAM which is an essential element in searching-based applications. Thus, there is a need to develop an optimal CAM core, which can be used for packet classification in modern re-configurable networking systems on FPGAs.…”