Distributed storage control unit for the Hitachi S-3800 multivector supercomputer

Abstract

This paper discusses the storage control unit of the Hitachi S-3800 supercomputer series, which is capable of achieving 8 GFLOPS in each of up to four shared-memory multiprocessors.This storage control unit is distributed to the V-SCS (vector-processor-side storage control units) and the M-SCS (main-storage-side storage control units), and achieves 128 gigabytes per second of total memory throughput. This distributed storage control unit supports scalability with increases in the number of processors and segmented parallel pipelines, simply by reconnecting the flat cables between the V-SCS and M-SCS. The distributed storage control unit also facilitated high sustained memory throughput for all types of vector-load and -store instructions. It features three new storage control schemes. (1) A hierarchical request-identification-number assignment scheme, which allows independent parallel memory access control in the V-SCS and M-SCS, This also enhances the indirect memory access performance.(2) A multistage address modification scheme, which achieves conflict-free constant-stride parallel memory access in both the V-SCS and M-SCS.(3) An instruction-based variable priority scheme, which achieves stable high memory throughput independent of other programs executed on the other processors. Results of performance measurements show the benefit of these schemes in the scalable distributed storage control unit for the S-3800 series.

Increasing the effective bandwidth of complex memory systems in multivector processors

“…Buffers allow the requesting processor to keep sending requests without waiting, but this technique requires labeling the memory references as they can be serviced out-of-order, and they must be ordered before being used by the processor. The labelling requires a wide path to the memory system as the tag must be sent along with the request [6][7] [8]; this increases the cost of the interconnection network. Also, the use of buffers can imply the presence of conflicts in the return-path to the processor [9].…”