Divide-and-Conquer Matrix Inversion for Linear MMSE Detection in SDR MIMO Receivers

Eberli, Stefan; Cescato, Davide; Fichtner, W.

doi:10.1109/norchp.2008.4738303

Cited by 21 publications

(14 citation statements)

References 15 publications

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“…sphere decoder) which can support different antenna configurations and modulation schemes [13] [14]. There are also a few which attempted to use flexible architectures [15] [16].…”

Section: Related Work and Contributionmentioning

confidence: 99%

“…In [16], a VLIW-like processor is used to implement the computation of the linear MMSE equalization matrix. The data path of the VLIW-based processor is equipped with a 2-way SIMD CMAC unit, complex ALU unit, and realvalued division unit.…”

Section: Related Work and Contributionmentioning

confidence: 99%

“…FLEXDET needs 16 cycles to compute the equalization, in which 13 cycles are used to compute the 4 × 4 matrix inversion from the corresponding 4×4 H matrix and 3 cycles [16] and an ASIC implementation [17] of a 4 × 4 linear MMSE detector. Because the comparison is on the equalization task, the area of the LLR block in FLEXDET is not considered.…”

Section: B Performancementioning

confidence: 99%

“…In [15] and [16], two flexible architectures of ASIP and VLIW are used for the computation of the linear MMSE equalization matrix. Both implementations apply direct matrix inversion for the computation.…”

Section: Flexible Implementationsmentioning

confidence: 99%

“…Implementations of matrix operations are seen using SIMD ASIPs [15] [16]. Due to the 1-dimension (1-d) feature of the SIMD data path in the computation and storage resources, it cannot fully explore the parallelism within matrix operations.…”

Section: Introductionmentioning

confidence: 99%

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FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection Using Reconfigurable ASIP

Chen

Minwegen

Hassan

et al. 2012

2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines

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This paper describes the implementation of a multi-mode MIMO detector based on the concept of partially reconfigurable ASIP (rASIP). The multi-mode detector can support three different detection algorithms which are the Maximum Ratio Combining, the linear Minimum Mean Square Error (MMSE) detection, and the MMSE Successive Interference Cancellation. The detection algorithms also support different antenna configurations and modulation schemes. The rASIP is based on a Coarse-Grained Reconfigurable Architecture (CGRA), which is designed for efficient architectural support of matrix operations. A matrix inversion algorithm, which is used for the preprocessing of different detection algorithms, is mapped on the CGRA. By integrating a processor with the CGRA, the variations in the control path of different algorithm configurations can be handled efficiently. To the best of our knowledge, we show, for the first time that, a CGRAbased multi-mode MIMO detection is extremely efficient and matches the performance of dedicated ASIC implementation.

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“…sphere decoder) which can support different antenna configurations and modulation schemes [13] [14]. There are also a few which attempted to use flexible architectures [15] [16].…”

Section: Related Work and Contributionmentioning

confidence: 99%

Section: Related Work and Contributionmentioning

confidence: 99%

Section: B Performancementioning

confidence: 99%

Section: Flexible Implementationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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