Dolmen: FPGA Swarm for Safety and Liveness Verification

Fournier, Émilien; Teodorov, Ciprian; Lagadec, Loïc

doi:10.23919/date54114.2022.9774528

Cited by 2 publications

(2 citation statements)

References 14 publications

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“…The underlying model-checker is OBP2, which can be interfaced with either EMI-UML or AnimUML (see below), to perform formal verification on the UML model executed by EMI-UML or AnimUML. The authors defined some generic interfaces between OBP2 and EMI execution engines such that they can use other model-checkers (tested with a FPGA-based model-cheker called Dolmen [FTL22]) or other controllers. EMI-UML has not been officially released neither put in open-source yet.…”

Section: Emi-uml Inmentioning

confidence: 99%

Formalizing UML State Machines for Automated Verification – A Survey

André

Liu

et al. 2023

ACM Comput. Surv.

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The Unified Modeling Language (UML) is a standard for modeling dynamic systems. UML behavioral state machines are used for modeling the dynamic behavior of object-oriented designs. The UML specification, maintained by the Object Management Group (OMG), is documented in natural language (in contrast to formal language). The inherent ambiguity of natural languages may introduce inconsistencies in the resulting state machine model. Formalizing UML state machine specification aims at solving the ambiguity problem and at providing a uniform view to software designers and developers. Such a formalization also aims at providing a foundation for automatic verification of UML state machine models, which can help to find software design vulnerabilities at an early stage and reduce the development cost. We provide here a comprehensive survey of existing work from 1997 to 2021 related to formalizing UML state machine semantics for the purpose of conducting model checking at the design stage.

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Section: Emi-uml Inmentioning

confidence: 99%

Formalizing UML State Machines for Automated Verification – A Survey

André

Liu

et al. 2023

ACM Comput. Surv.

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“…At the same time, the leakage power is only about 1.5uW. Unlike dynamic power consumption, it has nothing to do with frequency [9] . It is the power consumption of the circuit when the circuit has no jumps.…”

Section: Fpga Verification Platform Constructionmentioning

confidence: 99%

Design and verification of convolutional neural network accelerator

Xiang

Sui

Zhang

2023

International Conference on Signal Processing, Computer Networks, and Communications (SPCNC 2022)

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The existing software implementation schemes of Convolutional Neural Networks (CNN) cannot meet the requirements of computing performance and power consumption. To further improve the energy efficiency of the deep neural network, improve throughput and reduce power consumption, a hardware accelerator based on a convolutional neural network was designed, and a verification platform was built for it. The platform has good reusability and can flexibly complete the verification work of the target chip under various modes and configurations, and perform performance evaluation and functional correctness verification on the chip. Through the board-level verification results, this design reduces power consumption by 12.36% compared with similar accelerators and improves hardware resource utilization by 13.87% while keeping the same conditions as clock frequency and bus bit width.

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Dolmen: FPGA Swarm for Safety and Liveness Verification

Cited by 2 publications

References 14 publications

Formalizing UML State Machines for Automated Verification – A Survey

Formalizing UML State Machines for Automated Verification – A Survey

Design and verification of convolutional neural network accelerator

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