Domain-Specific Reconfigurable Array for Distributed Arithmetic

Khawam, S.; Arslan, Tughrul; Westall, F.

doi:10.1007/978-3-540-45234-8_139

Cited by 1 publication

(3 citation statements)

References 7 publications

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“…1 and described in [1] [2]. The communication between these arrays and the processor takes place through a system-on-chip.…”

Section: Reconfigurable Platform and Arraysmentioning

confidence: 99%

“…To overcome this problem, the authors recently introduced in [1] and [2] a novel reconfigurable platform that provides a compromise between performance, speed, power-consumption and flexibility when implementing such complex algorithms. The reconfigurable system uses domain-specific programmable arrays that are optimized for the target computations, such as ME or DCT.…”

Section: Introductionmentioning

confidence: 99%

“…The array presented in [1] targeting ME calculations showed a reduction of around 75% in power consumption when compared to generic FPGAs, while the area is reduced by 45% and timing improved by 23%. In [2] the same structure is used to design an array for Distributed Arithmetic (DA) calculations: the array provides a 38% reduction in power consumption, 14% in area and 54% decrease in the maximum operating frequency.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Efficient implementations of mobile video computations on domain-specific reconfigurable arrays

Khawam

Baloch

Pai

et al. 2004

Proceedings Design Automation and Test in Europe Conference and Exhibition DATE-04

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Mobile video processing as defined in standards like contains a number of timeconsuming computations that cannot be efficiently executed on current hardware architectures. The authors recently introduced a reconfigurable SoC platform that permits a low-power, high-throughput and flexible implementation of the motion estimation and DCT algorithms. The computations are done using domainspecific reconfigurable arrays that have demonstrated up to 75% reduction in power consumption when compared to generic FPGA architecture, which makes them suitable for portable devices. This paper presents and compares different configurations of the arrays to efficiently implementing DCT and motion estimation algorithms. A number of algorithms are mapped into the various reconfigurable fabrics demonstrating the flexibility of the new reconfigurable SoC architecture and its ability to support a number of implementations having different performance characteristics

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“…1 and described in [1] [2]. The communication between these arrays and the processor takes place through a system-on-chip.…”

Section: Reconfigurable Platform and Arraysmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%