Don’t care filling for power minimization in VLSI circuit testing

Maiti, T. K.; Chattopadhyay, Santanu

doi:10.1109/iscas.2008.4541998

Cited by 7 publications

(3 citation statements)

References 12 publications

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“…Based on the operation of a state machine, [28] elucidates a comprehensive frame for probability-based primary-input dominated X-filling methods to minimize the total weighted switching activity (WSA) during the scan capture operation. The work in [29] describes the effect of do not care filling of the patterns generated via automated test pattern generators, to make the patterns consume lesser power. It presents a tradeoff in the dynamic and static power consumption.…”

Section: Do Not Care Bitmentioning

confidence: 99%

Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

2011

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Test data compression is the major issues for the external testing of IP core-based SoC. From a large pool of diverse available techniques for compression, run length-based schemes are most appropriate for IP cores. To improve the compression and to reduce the test power, the test data processing schemes like "don't care bit filling" and "reordering" which do not require any modification in internal structure and do not demand use of any test development tool can be used for SoC-containing IP cores with hidden structure. The proposed "Weighted Transition Based Reordering-Columnwise Bit Filling-Difference Vector (WTR-CBF-DV)" is a modification to earlier proposed "Hamming Distance based Reordering-Columnwise Bit Filling and Difference vector." This new method aims not only at very high compression but also aims at shift in test power reduction without any significant on-chip area overhead. The experiment results on ISCAS89 benchmark circuits show that the test data compression ratio has significantly improved for each case. It is also noteworthy that, in most of the case, this scheme does not involve any extra silicon area overhead compared to the base code with which it used. For few cases, it requires an extra XOR gate and feedback path only. As application of this scheme increases run length of zeroes in test set, as a result, the number of transitions during scan shifting is reduced. This may lower scan power. The proposed scheme can be easily integrated into the existing industrial flow.

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Section: Do Not Care Bitmentioning

confidence: 99%

Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

2011

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“…Based on the operation of a state machine, [17] elucidates a comprehensive frame for probability-based primary-inputdominated X-filling methods to minimize the total weighted switching activity (WSA) during the scan capture operation. The authors in [18] describe the effect of do not care filling of the patterns generated via automated test pattern generators, to make the patterns consume lesser power. It presents a tradeoff in the dynamic and static power consumption.…”

Section: Exploring the Do Not Carementioning

confidence: 99%

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

2011

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Test power is the major issue for current generation VLSI testing. It has become the biggest concern for today's SoC. While reducing the design efforts, the modular design approach in SoC (i.e., use of IP cores in SoC) has further exaggerated the test power issue. It is not easy to select an effective low-power testing strategy from a large pool of diverse available techniques. To find the proper solutions for test power reduction strategy for IP core-based SoC, in this paper, starting from the terminology and models for power consumption during test, the state of the art in low-power testing is presented. The paper contains the detailed survey on various power reduction techniques proposed for all aspects of testing like external testing, Built-In Self-Test techniques, and the advances in DFT techniques emphasizing low power. Further, all the available low-power testing techniques are strongly analyzed for their suitability to IP core-based SoC.

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“…Moreover, Hamming distance reduction does not ensure leakage power minimization. In this direction, in [14] a different heuristic has been proposed. It uses Fiduccia-Mattheyses (FM) algorithm to fill X's in such a way that reduces both leakage and dynamic power.…”

Section: Introductionmentioning

confidence: 99%

Efficient Don't Care Filling for Power Reduction during Testing

Kundu

Chattopadhyay

2009

2009 International Conference on Advances in Recent Technologies in Communication and Computing

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Power consumption during test mode is much higher than in normal mode of operation. This paper addresses issue of assigning suitable values to the unspecified bits (don't care) in the test patterns so that both static and dynamic power consumption during testing is reduced. We have used a Genetic Algorithm based heuristic to fill the don't cares. Our approach produces an average percentage improvement of 31.9, 37.0, and 37.7 in dynamic power and 3.0, 7.4, and 5.3 leakage power over 0-fill, 1-fill, and MT-fill algorithms for don't care filling, considering the test patterns having unspecified bits in ISCAS'89 benchmark suite.

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Don’t care filling for power minimization in VLSI circuit testing

Cited by 7 publications

References 12 publications

Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

Efficient Don't Care Filling for Power Reduction during Testing

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