Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

Abstract

Test data compression is the major issues for the external testing of IP core-based SoC. From a large pool of diverse available techniques for compression, run length-based schemes are most appropriate for IP cores. To improve the compression and to reduce the test power, the test data processing schemes like "don't care bit filling" and "reordering" which do not require any modification in internal structure and do not demand use of any test development tool can be used for SoC-containing IP cores with hidden structure. The proposed "Weighted Transition Based Reordering-Columnwise Bit Filling-Difference Vector (WTR-CBF-DV)" is a modification to earlier proposed "Hamming Distance based Reordering-Columnwise Bit Filling and Difference vector." This new method aims not only at very high compression but also aims at shift in test power reduction without any significant on-chip area overhead. The experiment results on ISCAS89 benchmark circuits show that the test data compression ratio has significantly improved for each case. It is also noteworthy that, in most of the case, this scheme does not involve any extra silicon area overhead compared to the base code with which it used. For few cases, it requires an extra XOR gate and feedback path only. As application of this scheme increases run length of zeroes in test set, as a result, the number of transitions during scan shifting is reduced. This may lower scan power. The proposed scheme can be easily integrated into the existing industrial flow.

Selective compression technique using Variable-to-Fixed coding

“…The Indexing and Encoding, and hence the final V -F code word, is obtained, as was explained by the example. The amount of compression using the V -F codes can be computed as follows, as was given in [13]: CR%= (TD-TE/TD)*100…”

A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power

“…These techniques can be applied during external testing or deterministic BIST. Weighted transition based reordering was proposed in [5]. One such scheme [25] reorders the scan cells such that the test sequence shifted in has the minimum switching activity during test application.…”

“…Another major problem faced in system-on-chip (SOC) test integration is test power. Built-in self-test (BIST), [4][5][6] methodology reduces the need for expensive automatic test equipment (ATE). Though numerous methods are presented in literature so far, there are only few methods that handle both the issues of increased data volume and power dissipation simultaneously during testing.…”

“…It was shown in [5] that the use of appropriate reordering scheme combined with FDR code resulted in a considerable increase in compression ratio. It was shown in [5] that the use of appropriate reordering scheme combined with FDR code resulted in a considerable increase in compression ratio.…”

Improvement in error resilience for compressed VLSI test data using Hamming code based technique

“…Among such various test data compression method like broadcast scan based methods, linear decompression based methods and the code based methods, the code based compression method finds the most suitable for IP cores where the internal architecture of core is hidden from system Integrator. [9].…”