Double pattern EDA solutions for 32nm HP and beyond

Bailey, George E.; Tritchkov, Alexander; Park, Jea-Woo; Li, Hong; Wiaux, Vincent; Hendrickx, Eric; Verhaegen, Staf; Xie, Peng; Versluijs, Janko

doi:10.1117/12.712773

Cited by 52 publications

(35 citation statements)

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“…In gate-related failure analysis, overlay in just one direction is considered since gates are presumably unidirectional. Moreover, we assume all layers are aligned to a reference alignment mark on substrate 7 and overlay between different layers and the reference layer to be independent 8 . The overall POS from overlay is then calculated as the product of POS from independent overlay errors.…”

Section: Manufacturabilitymentioning

confidence: 99%

“…Each of these has challenging implications for layout methodologies and design rules (DRs). Resolution enhancement techniques (RETs) and other patterning solutions such as immersion and doublepatterning technology (DPT), off-axis illumination (OAI), sub-resolution assist features (SRAFs), and phase-shift mask (PSM) require additional layout-restrictive DRs [5][6][7][8][9][10][11]. Therefore, early assessment of design restrictions imposed by technological choices is absolutely essential.…”

Section: Introductionmentioning

confidence: 99%

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DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

Ghaida

Gupta

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Design rules have been the primary contract between technology developers and designers and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. The framework essentially creates a virtual standard-cell library and performs the evaluation based on the virtual layouts. Due to the focus on the exploration of rules at an early stage of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). Such a framework can be used to co-evaluate and co-optimize design rules, patterning technologies, layout methodologies, and library architectures.

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Section: Manufacturabilitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

Ghaida

Gupta

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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show abstract

“…Each of these has challenging implications for layout methodologies and design rules (DRs). Resolution enhancement techniques (RETs) and other patterning solutions such as immersion and double-patterning lithography (DPL), off-axis illumination (OAI), sub-resolution assist features (SRAFs), and phase-shift mask (PSM) require additional layout-restrictive DRs [5][6][7][8][9][10][11]. Therefore, early assessment of design restrictions imposed by technological choices is absolutely essential.…”

Section: Introductionmentioning

confidence: 99%

A framework for early and systematic evaluation of design rules

Ghaida

Gupta

2009

Proceedings of the 2009 International Conference on Computer-Aided Design

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Abstract-Design rules have been the primary contract between technology and design and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. Due to the focus on co-exploration in early stages of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). The framework is used to efficiently co-evaluate several debatable rules (evaluation for a 104-cell library takes 20 minutes). Results show that: a) diffusionrounding mainly from diffusion power-straps is a dominant source of variability, b) cell-area overhead of fixed gate-pitch implementation compared to 1D-poly implementation is tolerable (5%) given the improvement in variability, and c) 1D-poly restriction, which improves manufacturability and variability, has almost no area overhead compared to 2D-poly. In addition, we explore gate-spacing rules using our evaluation framework. This exploration yields almost identical values as those of a commercial 65nm process, which serves as a validation for our approach.

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“…To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. such as [4] and [5].…”

Section: Introductionmentioning

confidence: 99%

A matching based decomposer for double patterning lithography

Chu

2010

Proceedings of the 19th International Symposium on Physical Design

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Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain distance from each other on each layer onto two masks instead of one mask in traditional lithography. In this paper, we prove that the conflict graph used to model DPL conflicts in layout is a planar graph. Based on the planarity of the conflict graph, we propose a new face merging based framework which formulates DPL decomposition as a problem of pairing odd faces to simultaneously minimize the number of stitches generated and conflicts to eliminate. We employ partitioning and simplification techniques to reduce the problem size and use an O(n 3 ) time maximum weighted matching algorithm to generate an optimal DPL decomposition.

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Double pattern EDA solutions for 32nm HP and beyond

Cited by 52 publications

References 0 publications

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

A framework for early and systematic evaluation of design rules

A matching based decomposer for double patterning lithography

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