Double patterning process with freezing technique

Wakamatsu, Goji; Anno, Yusuke; Hori, Masafumi; Kakizawa, Tomohiro; Mita, Michihiro; Hoshiko, Kenji; Shioya, Takeo; Fujiwara, Koichi; Kusumoto, Shiro; Yamaguchi, Yoshikazu; Shimokawa, Tsutomu

doi:10.1117/12.814073

Cited by 25 publications

(16 citation statements)

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“…Design Target Imaged Pattern ∑ (1) , =1, 2, …n) (2) and are the averaged and maximum image edge errors relative the critical shape for all imaged contacts in the three sub-patterns, shown in figures 4 and 5. That is, each simulated exposure of the pattern shown in the figures yields one value of and one value of .…”

Section: Critical Shape Centered On Design Targetmentioning

confidence: 99%

“…However, to fabricate smaller IC patterns at higher pattern densities with 193i lithography, multipatterning and multi-exposure lithographic techniques have been adopted [2][3][4] . Given the overlay requirements for multi-patterning, stringent control of the pattern placement becomes even a greater challenge, with edge placement error (EPE) a key performance metric.…”

Section: Introductionmentioning

confidence: 99%

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Lithographic imaging-driven pattern edge placement errors at 10nm node

et al. 2016

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Demand for ever increasing level of microelectronics integration continues unabated, driving the reduction of the integrated circuit critical dimensions, and escalating requirements for image overlay and pattern dimension control. The challenges to meet these demands are compounded by requirement that pattern edge placement errors be at single nanometer levels. Layout design together with the patterning tools performance play key roles in determining location of the pattern edges at different device layers. However, complexities of the layout design often lead to stringent tradeoffs for viable optical proximity correction and imaging strategy solutions. As a result, in addition to scanner overlay performance, pattern imaging plays a key role in the pattern edge placement. The imaging contributes to edge displacement by impacting the image dimensions and by shifting the images relative to their target locations. In this report we discuss various aspects of advanced image control at 10 nm integrated circuit design rules. We analyze the impact of pattern design and scanner performance on pattern edges. We present an example of complex, three step litho-etch patterning involving immersion scanners. We draw conclusion on edge placement control when complex images interact with wafer topography.

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Section: Critical Shape Centered On Design Targetmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Lithographic imaging-driven pattern edge placement errors at 10nm node

et al. 2016

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“…1. Another reason is the circuit layout needs to satisfy the restrictive poly pitch due to the photolithography limitation in the advanced technologies [23][24][25][26], as shown in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

Source/Drain Series Resistance Extraction in HKMG Multifin Bulk FinFET Devices

2015

IEEE Trans. Semicond. Manufact.

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Effective extraction of source/drain (S/D) series resistances is a challenging task owing to poor epi-growth and non-uniform distribution of current density in S/D, critical limitation of restrictive design rule, ultra-thin contact film, and complicated 3D FinFET structure. In this paper, we report a test structure for measurement of linear and non-linear S/D series resistances. This technique enables us to evaluate each component of S/D series resistances resulting from the S/D contact, the S/D epi-growth fin, the S/D extension, and the channel gate, respectively. The S/D series resistance for fins on different layout location of the same diffusion is characterized and modeled by connection with a specified S/D contact on it. Furthermore, the S/D series resistance of each fin can be analytically calculated, respectively, by swapping the S/D bias condition. The proposed test structure and extraction technique provides a robust monitoring tool to diagnose a process weak point of the 16-nm multi-fin high-κ/metal gate bulk FinFET devices.

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“…Double patterning lithography (DPL) is the most promising alternative to generate the required lithography resolution. Litho-etch-litho-etch (LELE) [1], selfaligned double patterning (SADP) [2], and litho-freeze-lithoetch (LFLE) [3] methods are the most popular DPL processes. Each of DPL methods requires layout decomposition before manufacturing [4][5].…”

Section: Introductionmentioning

confidence: 99%

Design optimization of 16-nm bulk FinFET technology via geometric programming

2014

2014 International Workshop on Computational Electronics (IWCE)

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Design rule is an important interface between design and manufacturing. It becomes more complex as the process advances to 16-nm and beyond. Current approaches to generate design rules are empirical shrink and lithographic simulation. However, it is time-consuming and costly to revise design rules for performance boost and yield improvement after design rules are frozen. Early performance gains in early design rule development without cost increase and yield loss will benefit semiconductor industry. In this work, we for the first time consider 16-nm bulk FinFET standard cell performance, yield, area, and layout style simultaneously to optimize design rules to meet ITRS by using geometric programming. Optical proximity correction, and electromagnetic field and circuit simulations are performed for objective function evaluation. The result achieves more than 100%-delay and 50%-yield improvement without area change by this systematic and statistical approach.

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Double patterning process with freezing technique

Cited by 25 publications

References 0 publications

Lithographic imaging-driven pattern edge placement errors at 10nm node

Lithographic imaging-driven pattern edge placement errors at 10nm node

Source/Drain Series Resistance Extraction in HKMG Multifin Bulk FinFET Devices

Design optimization of 16-nm bulk FinFET technology via geometric programming

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