Double precision floating-point arithmetic on FPGAs

Paschalakis, Stavros; Lee, P.

doi:10.1109/fpt.2003.1275775

Cited by 29 publications

(11 citation statements)

References 4 publications

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“…For double precision, a new operation starts every 8 cycles instead of every cycle. Similar to divide, previous implementations of floating-point square root [Li and Chu 1997;Lee and Burgess 2002;Wang and Nelson 2003;Paschalakis and Lee 2003] all use simple digit serial algorithms.…”

Section: Related Workmentioning

confidence: 98%

“…However, it has long latency due to the iterative nature of the algorithm. A number of works [Lee and Burgess 2002;Wang and Nelson 2003;Paschalakis and Lee 2003;Underwood 2004;Govindu et al 2005;Thakkar and Ejnioui 2006] support IEEE single and double precision floating-point format. However, these designs use a digit-recurrence algorithm and exhibit long latency.…”

Section: Related Workmentioning

confidence: 99%

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VFloat

Xiao-jun¹,

Leeser

2010

ACM Trans. Reconfigurable Technol. Syst.

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Optimal reconfigurable hardware implementations may require the use of arbitrary floating-point formats that do not necessarily conform to IEEE specified sizes. We present a variable precision floating-point library (VFloat) that supports general floating-point formats including IEEE standard formats. Most previously published floating-point formats for use with reconfigurable hardware are subsets of our format. Custom datapaths with optimal bitwidths for each operation can be built using the variable precision hardware modules in the VFloat library, enabling a higher level of parallelism. The VFloat library includes three types of hardware modules for format control, arithmetic operations, and conversions between fixed-point and floating-point formats. The format conversions allow for hybrid fixed-and floating-point operations in a single design. This gives the designer control over a large number of design possibilities including format as well as number range within the same application. In this article, we give an overview of the components in the VFloat library and demonstrate their use in an implementation of the K-means clustering algorithm applied to multispectral satellite images.

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Section: Related Workmentioning

confidence: 98%

Section: Related Workmentioning

confidence: 99%

VFloat

Xiao-jun¹,

Leeser

2010

ACM Trans. Reconfigurable Technol. Syst.

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“…These modes are implemented by extending the relevant significands by three bits beyond their Least Significant Bit (LSB) L. These bits are referred to, from the most significant to the least significant, as "guard" (g), "round" (r) and "sticky" (st). The first two are normal extension bits, while the last one is the logical OR of all the bits that are lower than the r bit [13,14]. There are two cases:…”

Section: Rounding and Normalizingmentioning

confidence: 99%

Floating-Point Matrix Product on FPGA

Bensaali¹,

Amira²,

Sotudeh³

2007

2007 IEEE/ACS International Conference on Computer Systems and Applications

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The nature of some scientific computing applications involves performing complex tasks repeatedly on floatingpoint data, often under real-time requirements. Therefore, high performance systems are required by the developers for fast computations. Many researchers have begun to recognize the potential of reconfigurable hardware such as field-programable gate arrays in implementing floatingpoint arithmetic. In this paper a floating-point adder and multiplier are presented. The proposed cores are used as basic components for the implementation of a parallel floatingpoint matrix multiplier designed for 3D affine transformations. The cores have been implemented on recent FPGA devices. The performance in terms of area/speed of the proposed architectures has been assessed and has shown that they require less area and can be run with a higher frequency when compared with existing systems.

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“…In this paper, the pipelined designs of a double precision floating point divider and square root unit are presented. These two units are all IEEE 754 compliant based on the sequential designs presented in [5]. The pipelining of these units is based on unrolling the iterations of the digit recurrence computations and optimizing the operations within each unrolled iteration.…”

Section: Introductionmentioning

confidence: 99%

Pipelining of double precision floating point division and square root operations

Thakkar

Ejnioui

2006

Proceedings of the 44th Annual Southeast Regional Conference

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1Space applications rely increasingly on high data rate DSP algorithms. These algorithms use double precision floating point arithmetic operations. While most DSP applications can be compiled on DSP processors, high data rate DSP computations require novel implementation technologies to support their high throughputs. Only recently, gate densities in FPGAs have reached a level which makes them attractive platforms to implement compute-intensive DSP applications. In this context, this paper presents the sequential and pipelined designs of a double precision floating point divider and square root unit on FPGAs. Contrary to pipelined parallel implementations, the pipelining of these units is based on unrolling the iterations in low-radix digit recurrence algorithms. These units are mapped on generic FPGA reconfigurable fabric without taking advantage of any advanced architectural components available in high capacity FPGAs. The implementations of these designs show that their performances are comparable to, and sometimes higher than, the performances of non-iterative designs based of high radix numbers. The iterative divider and square root unit occupy less than 1% of an XC2V6000 FPGA chip while their pipelined counterparts can produce throughputs that reach the 100 MFLOPS mark by consuming a modest 8% of the chip area.

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Double precision floating-point arithmetic on FPGAs

Cited by 29 publications

References 4 publications

VFloat

VFloat

Floating-Point Matrix Product on FPGA

Pipelining of double precision floating point division and square root operations

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