Double raised source/drain transistor with 50 nm gate length on 17 nm UTF-SOI for 1.1 μm/sup 2/ embedded SRAM technology

Oh, Chang Bong; Oh, Man Hwan; Kang, Hee Sung; Park, Chang Hyun; Oh, Byung Jun; Kim, Yoon Hae; Rhee, Hwa Sung; Kim, Young Wug; Suh, Kang-Deog

doi:10.1109/iedm.2003.1269159

Cited by 3 publications

(1 citation statement)

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“…However, with SNM ∼ 140 mV and I wr ∼ 15 µA, the 2WL 6-T SRAM cell shows promising performance down to V DD = 0.5 V, demonstrating excellent scalability with power supply. Figure 12 compares our projected SNM values for the 2WL 6-T SRAM cell with state-of-the-art experimental data for SOI/SON [56][57][58][59][60][61][62][63][64], DG/FinFETs [65][66][67][68][69][70][71] and multibridge channel (MBC) FET [72][73][74] technologies over a wide range of gate lengths and supply voltages. Our optimized lowleakage SRAM cell (based on double-gate FET) fits in very well with the SNM trend emerging from the experimental data of DG/FinFETs.…”

Section: Valuementioning

confidence: 99%

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

Rashmi

Kranti

Armstrong

2008

Semicond. Sci. Technol.

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2008). 6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology. Semiconductor Science and Technology, 23 (7), [075049]. https://doi. AbstractThe impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/σ ) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM ∼ 162 mV, I wr ∼ 35 µA and low I leak ∼ 70 pA at V DD = 0.6 V, while maintaining SNM ∼ 30%V DD over the supply voltage (V DD ) range of 0.4-0.9 V.

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