6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

Abstract

2008). 6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology. Semiconductor Science and Technology, 23 (7), [075049]. https://doi. AbstractThe impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/σ ) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM ∼ 162 mV, I wr ∼ 35 µA and low I leak ∼ 70 pA at V DD = 0.6 V, while maintaining SNM ∼ 30%V DD over the supply voltage (V DD ) range of 0.4-0.9 V.

Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel

“…Previous studies on underlap design in MOSFETs have shown significant improvement in digital and analog/RF metrics [21][22][23].…”

Large-Scale SRAM Variability Characterization in 45 nm CMOS

“…24(b) shows a large cloud near the y axis at high WWTV and low values, corresponding to the values captured due to standby retention failures. The excellent agreement between extracted and large-scale read/write margin measurements suggest that read/write metrics measured using 11 The zero crossing of the WWTV measurements does not correspond to V = 0:6 V due to the application of a 100 mV WL weak write. direct bit-line characterization, which are easier to model than and can be fitted to simple Gaussian distributions, can be used to estimate .…”

“…This effectively measures current minus current. The writeability current [10], [11], , is defined as the minimum measured current past the inverter trip point [ Fig. 1(e)].…”

A highly stable and low‐cost 12T radiation hardened SRAM cell design for aerospace application

“…This effectively measures the current of the access transistor minus the current of the pull‐up transistor. The write‐ability current I W , 27 is defined as the least measured current past the trip point of the inverter Q. A bigger I W indicates a more writeable cell, whereas I W ≤ 0 indicates a write failure.From Figure 5D, we can see that the I W of our proposed HSLC12T cell is the largest of all the other compared radiation hardened cells, which is because in the write operation, the signal affects not only nodes Q and QN but also the other two nodes S0 and S1, facilitating the writing operation through feedback.…”