DPT restricted design rules for advanced logic applications

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

Badr

Gupta

et al. 2014

Abstract-Co-development of design rules and layout methodologies is the key to successful adoption of a technology. In this work, we propose Chip-level Design Rule Evaluator (ChipDRE), the first framework for systematic evaluation of design rules and their interaction with layouts, performance, margins and yield at the chip scale (as opposed to standard cell-level). A "good chips per wafer" metric is used to unify area, performance, variability and yield. The framework uses a generated virtual standard-cell library coupled with a mix of physical design, semiempirical, and machine-learning-based models to estimate area and delay at the chip level. The result is a unified design-quality estimate that can be computed fast enough to allow using ChipDRE to optimize a large number of complex design rules. For instance, a study of well-to-active spacing rule reveals a non-monotone dependence of rule value to chip area (although the dependence to cell area is monotone) due to delay changes coming from well-proximity effect.

Section: B Model Formulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Comprehensive die-level assessment of design rules and layouts

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

Badr

Gupta

et al. 2014

“…For this approach to be examined, a method for studying the effect of rules on MP conflicts as well as layout area is needed. An explicit layout generation based approach such as [20], though possible, is cumbersome, inflexible and not generalizable for the purpose of assessment of the inherent "DP-friendliness" of rules.…”

Section: Role Of Design In Mp Technology Developmentmentioning

confidence: 99%

Role of Design in Multiple Patterning: Technology Development, Design Enablement and Process Control

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

Gupta

2013

Abstract-Multiple-patterning optical lithography is inevitable for technology scaling beyond the 22nm technology node. Multiple patterning imposes several counter-intuitive restrictions on layout and carries serious challenges for design methodology. This paper examines the role of design at different stages of the development and adoption of multiple patterning: technology development, design enablement, and process control. We discuss how explicit design involvement can enable timely adoption of multi-patterning with reduced costs both in design and manufacturing.

“…Figure 9 shows a comparison between ROCcurves of our model, random guess, and a multivariate linear 6 One explanation for this is that including both horizontal and vertical congestion already captures the same information given by L and T-shapes. 7 We use hyperbolic tangent-sigmoid for the hidden-layer activation function and a linear function for the output-layer activation function. 8 Originally, outputs are decimal numbers because a linear function is used for the output activation function.…”

Section: Testing and Approach Validationmentioning

confidence: 99%

“…The work in [7] presents a flow for DP design rules optimization. The method consists of an optimization loop in which rules are modified, the layout is generated, and printability is analyzed.…”

Section: Introductionmentioning

confidence: 99%

A methodology for the early exploration of design rules for multiple-patterning technologies

Proceedings of the International Conference on Computer-Aided Design

Sahu

Kulkarni

et al. 2012

Abstract-Double/Multiple-patterning (DP/MP) lithography in a multiple litho-etch steps process is a favorable solution for technology scaling to the 20nm node and below. Mask-assignment conflicts represent the biggest challenge for MP and limiting them through design rules is crucial for the adoption of MP technology. In this paper, we offer a methodology for the early evaluation and exploration of layout and MP rules intended for speeding up the rules-development cycle. Using a novel wiringestimation method, we create layout estimates with fine-grained congestion prediction. MP-conflicts are then predicted using a machine-learning approach. In this work, we demonstrate the use of the method for double-patterning lithography in litho-etchlitho-etch process; the methodology is more general, however, and can be applied for other multiple-patterning technologies including tripe/multiple-patterning with multiple litho-etch steps, selfaligned double patterning (SADP), and directed self-assembly. Results of testing the methodology on standard-cell layouts show an 81% accuracy in DP-conflicts prediction. The methodology was then used to explore DP and layout rules and investigate their effects on DP-compatibility and layout area. The methodology allows for rules optimization; for example, pushing the minimum tip-to-side same-color spacing rule value from 1.7× to 1.5× the minimum side-to-side spacing design rule (i.e., from 110nm down to 90nm) would more than double the number of DP-compatible cells in the library.