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On the road to insertion of extreme ultraviolet (EUV) lithography into production at the 16 nm technology node and below, we are testing its integration into standard semiconductor process flows for 22 nm node devices.In this paper, we describe the patterning of two levels of a 22 nm node test chip using single-exposure EUV lithography; the other layers of the test chip were patterned using 193 nm immersion lithography. We designed a full-field EUV mask for contact and first interconnect levels using rule-based corrections to compensate for the EUV specific effects of mask shadowing and imaging system flare. The resulting mask and the 0.25-NA EUV scanner utilized for the EUV lithography steps were found to provide more than adequate patterning performance for the 22 nm node devices. The CD uniformity across the exposure field and through a lot of wafers was approximately 6.1% (3σ) and the measured overlay on a representative test chip wafer was 13.0 nm (x) and 12.2 nm (y). A trilayer resist process that provided ample process latitude and sufficient etch selectivity for pattern transfer was utilized to pattern the contact and first interconnect levels. The etch recipes provided good CD control, profiles and end-point discrimination.The patterned integration wafers have been processed through metal deposition and polish at the contact level and are now being patterned at the first interconnect level.

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In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography to pattern the first interconnect level (metal 1).This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip (product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity of 3.8 mJ/cm 2 , providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as evidenced by electrical test results.Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.