Drain Conductance Oscillations in Poly-Si Junctionless Nanowire Thin-Film Transistors

Kang, Tsung-Kuei; Peng, Yen-Hao

doi:10.1109/ted.2018.2879724

Cited by 3 publications

(4 citation statements)

References 20 publications

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“…Hereafter, this TFT device is called an "L-type double-gated" JL TFT. 29) The devices with 30 nanowires were measured in this paper and the I-V measurements were performed by an HP4155C semiconductor parameter analyzer.…”

Section: Methodsmentioning

confidence: 99%

Effect of transient behavior on off-state current in poly-Si junctionless nanowire thin-film transistor

Kang¹,

Hsu²,

Liu³

et al. 2020

Jpn. J. Appl. Phys.

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For forward sweeping of V GS, the unpredicted negative drain current is observed in our L-type double-gated junctionless transistor. This reveals that in addition to gate-induced drain leakage, there is an another mechanism that causes this negative drain current. According to some measurements, it is found that the negative drain current is related to the steep V GS transition, and the large reduction of hole density in the nanowire channel induces a transient negative drain current. Based on this mechanism, for reverse sweeping of V GS, the positive drain current is measured due to an increment of hole density in the nanowire channel. To explain the mechanism well, the hole density in the Si channel is simulated and an AC model is proposed. Finally, it is likely that the transient negative current of the drain is also affected by the gate transient current, besides the large reduction of hole density.

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Section: Methodsmentioning

confidence: 99%

Effect of transient behavior on off-state current in poly-Si junctionless nanowire thin-film transistor

Kang¹,

Hsu²,

Liu³

et al. 2020

Jpn. J. Appl. Phys.

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“…The electrons instability influences the grain boundaries potential, which causes oscillation in the drain conductance. This phenomenon is more critical in TFTs with double gates, since the higher mobility allows for the electrons to easily destroy the trapped ones, and increase the oscillation [81]. Designers can limit this phenomenon by increasing the doping concentration [76].…”

Section: Thin Filmmentioning

confidence: 99%

“…This device turned out to be the first one of a new generation of transistors. In the last decades, many other junctionless devices were proposed, which includes FinFET , Gate-All-Around (GAA) [24][25][26][27][28][29][30][31][32][33][34][35][36][37], Single Gate (SGJLT) [38][39][40][41][42][43][44][45][46][47][48][49][50], Double Gate (DGJLT) , Thin Film (TFT) [76][77][78][79][80][81][82][83][84][85][86], and Tunnel FET (TFET) [87][88][89][90][91][92][93][94][95][96][97]. Because most of the review papers on JLTs were published in 2010-2014…”

Section: Introductionmentioning

confidence: 99%

Junctionless Transistors: State-of-the-Art

2020

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Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as I o n / I o f f , D I B L , and S S , to highlight the advantages and disadvantages of each junctionless transistor category.

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“…Recently, the JLMOSFETs have received significant attention for their technological feasibility and theoretical modeling. In the last decades, several device architectures for JLMOSFETs were proposed, such as Thin Film JLMOSFET [5], [6], FinFET [7], [8], Tunnel FET [9], [10], gate-all-around (GAA) FET [11], [12], singlegate JLT (SG-JLT) [13], [14], double-gate JLMOSFETs (DG-JLMOSFETs) [15]- [18], etc. The DG-JLMOSFETs are becoming more promising due to their superior performances in high speed and low power applications [19].…”

Section: Introductionmentioning

confidence: 99%

Impact of Channel Thickness on the Performance of GaAs and GaSb DG-JLMOSFETs: An Atomistic Tight Binding Based Evaluation

Islam

Hasan²,

Islam

et al. 2021

IEEE Access

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In this paper, the performance of GaAs and GaSb based sub-10 nm double-gate junctionless metal-oxide-semiconductor field-effect transistors (DG-JLMOSFETs) have been studied for highperformance switching applications. The quantum transmitting boundary method (QTBM) has been considered for electron transport, and the band structures are accounted for sp3d5s * tight-binding modeling. The channel thickness, t ch is varied from 1.7 to 4.7 nm to evaluate the device figure of merits (FOMs). The thinner channel's device shows a lower OFF-state current, while the ticker channel device allows a higher ON-state current. The threshold voltage is approximately 0.4 V for GaAs DG-JLMOSFETs with t ch = 1.7 nm, whereas it reduces to ∼0.05 V for that of t ch = 4.7 nm. Similar characteristics have been shown in GaSb devices. Besides, a significant impact of t ch on the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) is found in GaSb DG-JLMOSFETs compared with those of GaAs devices. The devices show a higher leakage-power dissipation in both channel materials and low-intrinsic delay for thicker t ch due to a substantial amount of energy drop. The above results indicate that III-V-based DG-JLMOSFETs are very promising for next-generation high-performance switching technology.INDEX TERMS GaAs, GaSb, double gate, junctionless MOSFETs, nano-scaled device, short-channel effects (SCEs), high-performance switching.

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Drain Conductance Oscillations in Poly-Si Junctionless Nanowire Thin-Film Transistors

Cited by 3 publications

References 20 publications

Effect of transient behavior on off-state current in poly-Si junctionless nanowire thin-film transistor

Effect of transient behavior on off-state current in poly-Si junctionless nanowire thin-film transistor

Junctionless Transistors: State-of-the-Art

Impact of Channel Thickness on the Performance of GaAs and GaSb DG-JLMOSFETs: An Atomistic Tight Binding Based Evaluation

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