Drive current and threshold voltage control in vertical InAs wrap-gate transistors

Rehnstedt, C.; Thelander, Claes; Fröberg, Lars; Ohlsson, Björn; Samuelson, Lars; Wernersson, Lars‐Erik

doi:10.1049/el:20083188

Cited by 14 publications

(15 citation statements)

References 7 publications

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“…Electrical characterization of transistors with matrices of nanowires has shown that the drive current as well as the transconductance scales with the number of wires as expected [5]. This is essential as the control of the number of wires in the matrix provides a way to determine the drive current and the transconductance, corresponding to the gate width in planar technologies.…”

Section: Methodsmentioning

confidence: 92%

III/V Nanowire FETs for CMOS?

Wernersson

2008

ECS Trans.

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III/V MOS transistors are currently attracting considerable attention. The main driving force is that the advantageous transport properties in III/V materials are expected to increase the drive current in the MOS transistors. Major challenges for the III/V MOS technologies include the growth of high-quality III/V materials on Si substrates and the control of the MOS interface. Using the nanowire technology, we have recently demonstrated enhancement mode operation of 50 nm L g InAs nanowire wrap-gate transistors in a vertical configuration. They demonstrate a transconductance of 0.5 S/mm, an inverse sub-threshold slope of about 80 mV/dec., and an I on /I off ratio > 1000 for a drive voltage of V d =0.5 V. These results show promise for the use of nanowires in CMOS applications.

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Section: Methodsmentioning

confidence: 92%

III/V Nanowire FETs for CMOS?

Wernersson

2008

ECS Trans.

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“…3(e) demonstrate a room-temperature sub-threshold swing S = 300 mV/dec and on-off ratio of ∼ 10 4 , competitive with nanowire wrap-gate transistors, where sub-threshold swings typically range from 100 to 750 mV/dec. 28,[38][39][40][41][42] The same on-off ratio is achieved for SiO 2 -insulated back-gated devices using nanowires from the same growth shown in Supplementary Figure S8 Fabrication for this device began by defining arrays of fifteen 400 nm-wide, 30 nm-thick Ti/Au strips with 200 nm spacing. Nanowires were precisely placed on top of these strips, perpendicular to the strip orientation.…”

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confidence: 82%

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors

et al. 2018

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We report the development of nanowire field-effect transistors featuring an ultrathin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally coated nanowires, which we used to produce functional Ω-gate and gate-all-around structures. These give subthreshold swings as low as 140 mV/dec and on/off ratios exceeding 10 at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically treated nanowire surfaces, a feature generally not possible with oxides produced by atomic layer deposition due to the surface "self-cleaning" effect. Our results highlight the potential for parylene as an alternative ultrathin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties.

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“…2 that the depletion capacitance reaches zero under reverse bias, indicating that the nanowires are depleted. In this regime, the nanowire capacitor can be modeled as a simple radial MISFET device, 14 as shown in Fig. 4.…”

Section: B Modified Radial Misfet Modelmentioning

confidence: 99%

Doping Incorporation in InAs nanowires characterized by capacitance measurements

Astromskas

Storm

Karlström

et al. 2010

Journal of Applied Physics

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Sn and Se doped InAs nanowires are characterized using a capacitance-voltage technique where the threshold voltages of nanowire capacitors with different diameter are determined and analyzed using an improved radial metal-insulator-semiconductor field-effect transistor model. This allows for a separation of doping in the core of the nanowire from the surface charge at the side facets of the nanowire. The data show that the doping level in the InAs nanowire can be controlled on the level between 2×1018 to 1×1019 cm−3, while the surface charge density exceeds 5×1012 cm−2 and is shown to increase with higher dopant precursor molar fraction.

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Drive current and threshold voltage control in vertical InAs wrap-gate transistors

Cited by 14 publications

References 7 publications

III/V Nanowire FETs for CMOS?

III/V Nanowire FETs for CMOS?

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors

Doping Incorporation in InAs nanowires characterized by capacitance measurements

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