Dry etching of polysilicon with high selectivity using a chlorine-based plasma in an ECR reactor

Chang, Kow–Ming; Yeh, Ta Hsun; Wang, S. W.; Li, C. H.; Yang, Ji Yi

doi:10.1016/0254-0584(96)80042-3

Cited by 3 publications

(1 citation statement)

References 5 publications

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“…[10][11][12] Polycrystalline Si is usually made by casting, although because polycrystalline Si is used for gate electrodes in MOSFETs, and selective etching is being investigated. [13][14][15][16] Due to the requirements of high-aspect-ratio RIE, the number of polycrystalline Si parts is increasing. Polycrystalline Si used for RIE equipment parts is consumed and the changes in surface roughness affect RIE.…”

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confidence: 99%

Effect on Etch Rate and Surface Roughness of Crystal Orientation of Polycrystalline Silicon Used for Consumable Parts of Reactive Ion Etching Equipment

Matsumoto¹,

Honma²

2022

ECS J. Solid State Sci. Technol.

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Silicon is used for consumable parts in reactive ion etching (RIE) equipment because it generates fewer particles, which decrease the yield, than other materials. Polycrystalline silicon is usually used for top electrodes, especially in high-aspect-ratio RIE, to increase the wafer’s self-bias. In this study, the relationships among the crystal orientation of the polycrystalline silicon used in RIE equipment, grain size, grain boundary length, etch rate, and surface roughness were investigated. The grain size and the etch rate decreased as the percentage of Si(111) in the polycrystalline silicon increased. The grain size and etch rate for 47% Si(111) decreased to 66.4% and 84.7%, respectively, compared with 8% Si(111). Moreover, the grain boundary length and surface roughness increased as the percentage of Si(111) increased. The grain boundary length and surface roughness for 47% Si(111) increased by 1.8 and 19.6 times, respectively, compared with 8% Si(111). Therefore, as the percentage of Si(111) increased, the grain size and etch rate decreased, whereas the grain boundary length and surface roughness increased.

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confidence: 99%

Effect on Etch Rate and Surface Roughness of Crystal Orientation of Polycrystalline Silicon Used for Consumable Parts of Reactive Ion Etching Equipment

Matsumoto¹,

Honma²

2022

ECS J. Solid State Sci. Technol.

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Reliability Considerations for Advanced and Integrated LED Systems

Fan

2012

Solid State Lighting Reliability

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Coupling of equipment simulation and feature-scale profile simulation for dry-etching of polysilicon gate lines

Baer

Kunder

Evanschitzky

et al. 2010

2010 International Conference on Simulation of Semiconductor Processes and Devices

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We demonstrate the coupling of plasma reactor equipment simulation and feature-scale profile simulation for dry etching of silicon in a chlorine plasma. Equipment simulation delivers fluxes of ions and neutrals, as well as the angular characteristics of the ions. These quantities are fed into a feature-scale simulator based on a Monte Carlo approach for determining relevant quantities on the feature surface, i.e. the concentration of adsorbed neutrals and the number of removed silicon atoms due to chemical sputtering. Using the coupled simulation system, we are able to study the influence of equipment parameters on the resulting etching profiles. As an example, we show the etching of polysilicon for gate formation and determine profile variations according to different positions on the waf er and according to varying bias applied to the substrate in the etching reactor

show abstract

Dry etching of polysilicon with high selectivity using a chlorine-based plasma in an ECR reactor

Cited by 3 publications

References 5 publications

Effect on Etch Rate and Surface Roughness of Crystal Orientation of Polycrystalline Silicon Used for Consumable Parts of Reactive Ion Etching Equipment

Effect on Etch Rate and Surface Roughness of Crystal Orientation of Polycrystalline Silicon Used for Consumable Parts of Reactive Ion Etching Equipment

Reliability Considerations for Advanced and Integrated LED Systems

Coupling of equipment simulation and feature-scale profile simulation for dry-etching of polysilicon gate lines

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