Dual-band RF receiver chip-set for Galileo/GPS applications

Detratti, Marco; Lopez, E.; Perez, E.; Palacio, R.; Lobeira, M.

doi:10.1109/plans.2008.4569991

Cited by 9 publications

(3 citation statements)

References 11 publications

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“…To overcome the limitations mentioned above, extensive research on the CMOS (complementary metal-oxide semiconductor) integration of the dual-frequency radio frequency (RF) front-end for GNSS has been performed [13][14][15][16][17][18][19]. So far, most of the designs either offer only configurability between different bands of GNSS without the possibility of simultaneous multi-frequency reception of all constellations by a single chip [13,15,16,19] or they do not receive all bands from the most popular GNSS systems and focus only on L1/E1 and L5/E5a reception [14,17].…”

Section: Introductionmentioning

confidence: 99%

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

Borejko

Marcinek

Siwiec

et al. 2020

Sensors

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A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS (complementary metal-oxide semiconductor) process. The GNSS RF (radio frequency) front-end with baseband navigation engine is able to receive, simultaneously, Galileo (European Global Satellite Navigation System) E1/E5ab, GPS (US Global Positioning System) L1/L1C/L5, BeiDou (Chinese Navigation Satellite System) B1/B2, GLONASS (GLObal NAvigation Satellite System of Russian Government) L1/L3/L5, QZSS (Quasi-Zenith Satellite System development by the Japanese government) L1/L5 and IRNSS (Indian Regional Navigation Satellite System) L5, as well as all SBAS (Satellite Based Augmentation System) signals. The ability of the GNSS to detect such a broad range of signals allows for high-accuracy positioning. The whole SoC (system-on-chip), which is connected to a small passive antenna, provides precise position, velocity and time or raw GNSS data for hybridization with the IMU (inertial measurement unit) without the need for an external application processor. Additionally, user application can be executed directly in the SoC. It works in the −40 to +105 °C temperature range with a 1.5 V supply. The assembled test-chip takes 100 pins in a QFN (quad-flat no-leads) package and needs only a quartz crystal for the on-chip reference clock driver and optional SAW (surface acoustic wave) filters. The radio performance for both wideband (52 MHz) channels centered at L1/E1 and L5/E5 is NF = 2.3 dB, G = 131 dB, with 121 dBc/Hz of phase noise @ 1 MHz offset from the carrier, consumes 35 mW and occupies a 4.5 mm2 silicon area. The SoC reported in the paper is the first ever dual-frequency single-chip GNSS receiver equipped with a multi-core application microcontroller integrated with embedded flash memory for the user application program.

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Section: Introductionmentioning

confidence: 99%

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

Borejko

Marcinek

Siwiec

et al. 2020

Sensors

View full text Add to dashboard Cite

show abstract

“…17. The different central frequencies (15.902, 15.48, and 12.24 MHz) and bandwidths (2,4,9,10, and 20 MHz) can be provided for different working modes. In addition, all of the in-band ripples are less than 1 dB.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…Most GNSS RXs, published in the past have focused on the use of GPS/Galileo systems [4]- [9], which also can provide high-resolution location satisfying the two reasons above, but these RXs lack sufficient flexibility for processing all of the GNSS signals. Recently, several successful implementations of fully integrated GNSS RXs, including GPS/GLONASS/ Galileo/Compass systems have been reported in [10]- [12].…”

mentioning

confidence: 99%

Reconfigurable All-Band RF CMOS Transceiver for GPS/GLONASS/Galileo/Beidou With Digitally Assisted Calibration

et al. 2015

IEEE Trans. VLSI Syst.

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This paper presents a fully integrated reconfigurable all-band RF transceiver for GPS/GLONASS/ Galileo/Beidou in 55-nm CMOS. The transceiver incorporates three low-IF receivers (RXs) and one direct up-conversion BPSK transmitter (TX), which can be configured to receive any two global navigation satellite system (GNSS) signals or switched to process the Chinese Beidou(I) signals. A switching module is integrated to provide the connectivity between different RF front-end and IF channel (IFC), which will effectively simplify the design complexity of the IFC and save power consumption, while the GNSS signals are received. A flexible frequency plan with two frequency synthesizers is utilized to satisfy different local oscillator requirements of the transceiver. An optimized automatic frequency calibration scheme using an error compensation logic enables fast and high-precision calibration process for optimum phase-locked loop operation. Several digitally assisted calibration modules are integrated to ensure that the chip performance only shows a weak process, voltage and temperature (PVT) dependence. While drawing about 21.5-30.2 mA per RX channel from a 1.2-V supply, the RXs achieve an image rejection ratio more than 49 dB after I/Q mismatch calibration, an automatic gain control range of 88 dB, and an input-referred 1 dB compression point of better than −25 dBm with a minimum noise figure of about 2 dB. The output power of the TX is about 5 dBm with about 6% error vector magnitude (EVM) and 30-mA current from a 1.2-V supply. The whole transceiver consumes a die area of 2.8 × 3 mm 2 .

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Design of a dual-channel multi-mode GNSS receiver with a Σ Δ fractional-Nsynthesizer

Long¹,

Zhang²,

Yin³

et al. 2012

J. Semicond.

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A 72 mW highly integrated dual-channel multimode GNSS (global navigation satellite system) receiver with a † fractional-N synthesizer which covers GPS L1 and the Compass B1/B2/B3 band is presented. This chip was fabricated in a TSMC CMOS 0.18 m process and packaged in a 48-pin 3 3 mm 2 land grid array chip scale package. This work achieves NF 6 5.3 dB without an external LNA, channel gain D 105 dB for channel one (Compass B2 and B3 band), and channel gain D 110 dB for channel two (GPS L1 and Compass B1 band). Image rejection (IMRR) D 36 dB, phase noise is -115.9 dBc @ 1 MHz and -108.9 dBc @ 1 MHz offset from the carrier for the two channels separately. At the low power consumption, multibands of GNSS are compatible in one chip, which is easy for consumers to use, when two different navigation signals are received simultaneously.

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Dual-band RF receiver chip-set for Galileo/GPS applications

Cited by 9 publications

References 11 publications

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

Reconfigurable All-Band RF CMOS Transceiver for GPS/GLONASS/Galileo/Beidou With Digitally Assisted Calibration

Design of a dual-channel multi-mode GNSS receiver with a Σ Δ fractional-Nsynthesizer

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