Dual-Core Lockstep enhanced with redundant multithread support and control-flow error detection

Pena-Fernandez, M.; Serrano-Cases, Alejandro; Lindoso, Almudena; García-Valderas, M.; Entrena, Luis; Martínez-Álvarez, Antonio; Cuenca-Asensi, Sergio

doi:10.1016/j.microrel.2019.113447

Cited by 13 publications

(8 citation statements)

References 18 publications

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“…The underlying idea in MC fault-tolerant architectures [11], [12] is the migration of all the techniques used in SMT cores to multiple cores. A particular implementation of MC fault tolerance is represented by lock-stepped cores [12], [23], in which synchronized processor replicas execute the same instruction in the same clock cycle (or with a fixed-time separation of a few cycles) and the results of each instruction are compared in real-time.…”

Section: B Multi-core Processorsmentioning

confidence: 99%

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

et al. 2022

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Fault management in digital chips is a crucial aspect of functional safety. Significant work has been done on gate and microarchitecture level triple modular redundancy, and on functional redundancy in multi-core and simultaneous-multi-threading processors, whereas little has been done to quantify the fault tolerance potential of interleaved-multi-threading. In this study, we apply the temporal-spatial triple modular redundancy concept to interleaved-multi-threading processors through a design solution that we call Buffered triple modular redundancy, using the soft-core Klessydra-T03 as the basis for our experiments. We then illustrate the quantitative findings of a large fault-injection simulation campaign on the fault-tolerant core and discuss the vulnerability comparison with previous representative fault-tolerant designs. The results show that the obtained resilience is comparable to a full triple modular redundancy at the cost of execution cycle count overhead instead of hardware overhead, yet with higher achievable clock frequency.INDEX TERMS Circuit faults, digital integrated circuits, fault detection, fault tolerant computing, field programmable gate arrays, microprocessors, multithreading, radiation hardening (electronics), redundancy, robustness.Open Access funding provided by 'Università degli Studi di Roma ''La Sapienza''' within the CRUI CARE Agreement

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Section: B Multi-core Processorsmentioning

confidence: 99%

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

et al. 2022

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“…This is the case of [29] in which an external IP verifies the state of two cores and is able to trigger interrupts in a multicore system. In [30] a relaxed synchronization is presented to stablish hardening strategy for Cortex-A9. In this case, multiple threads with their own stack are used, but without the support of an Operating System (OS).…”

Section: Related Workmentioning

confidence: 99%

“…In this case, multiple threads with their own stack are used, but without the support of an Operating System (OS). Additionally, the approach in [30] is hybrid and uses an external IP connected to the microprocessor's trace interface to control the execution flow.…”

Section: Related Workmentioning

confidence: 99%

Radiation Testing of a Multiprocessor Macrosynchronized Lockstep Architecture With FreeRTOS

Avilés

Lindoso

Belloch

et al. 2022

IEEE Trans. Nucl. Sci.

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Nowadays, high performance microprocessors are demanded in many fields, including those with high reliability requirements. Commercial microprocessors present a good tradeoff between cost, size and performance, albeit they must be adapted to satisfy the reliability requirements when they are used in harsh environments. This work presents a high-end multiprocessor hardened with a macro synchronized lockstep and additional protections. A commercial dual core ARM cortex A9 has been used as case study and a complete hardened system has been developed. Evaluation of the proposed hardened system has been accomplished with exhaustive fault injection campaigns and proton irradiation. The hardening approach has been accomplished for both baremetal applications and OS-based. The hardened system has demonstrated high reliability in all performed experiments with error coverage up to 99.3% in the irradiation experiments. Experimental irradiation results demonstrate a cross-section reduction of two orders of magnitude.

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“…The use of the trace interface for error detection in ARM microprocessors has recently been proposed and demonstrated, showing good error detection [6]. The capabilities of the trace interface as an observation point for error detection have also been adapted to multicore systems in [12].…”

Section: Background and Related Workmentioning

confidence: 99%

Error Detection and Mitigation of Data-Intensive Microprocessor Applications Using SIMD and Trace Monitoring

Pena-Fernandez

Lindoso

Entrena

et al. 2020

IEEE Trans. Nucl. Sci.

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This work proposes a software error mitigation approach that uses the SIMD coprocessor to accelerate computation over redundant data. In addition, an external IP connected to the microprocessor's trace interface is used to detect errors that are difficult to cover with software-implemented techniques. The proposed approach has been implemented in an ARM microprocessor and an irradiation campaign with neutrons has been carried out at Los Alamos National Laboratory. Experimental results demonstrate the high error coverage (more than 99.9%) of the proposed approach. The neutron cross section of errors that were not corrected nor detected was reduced by more than three orders of magnitude.

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Dual-Core Lockstep enhanced with redundant multithread support and control-flow error detection

Cited by 13 publications

References 18 publications

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

Radiation Testing of a Multiprocessor Macrosynchronized Lockstep Architecture With FreeRTOS

Error Detection and Mitigation of Data-Intensive Microprocessor Applications Using SIMD and Trace Monitoring

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