Convolutional computation kernels are fundamental to today's edge computing applications. Interleaved-Multi-Threading (IMT) processor cores are an interesting approach to pursue the highest energy efficiency and lowest hardware cost in edge computing systems, yet they need hardware acceleration schemes to deal with heavy computational workloads like convolutional algorithms. Following a vector approach to accelerate convolutions, this study explores possible alternatives to implement vector coprocessing units in IMT cores, showing the application-dependence of the optimal balance among the hardware architecture parameters.

Fault management in digital chips is a crucial aspect of functional safety. Significant work has been done on gate and microarchitecture level triple modular redundancy, and on functional redundancy in multi-core and simultaneous-multi-threading processors, whereas little has been done to quantify the fault tolerance potential of interleaved-multi-threading. In this study, we apply the temporal-spatial triple modular redundancy concept to interleaved-multi-threading processors through a design solution that we call Buffered triple modular redundancy, using the soft-core Klessydra-T03 as the basis for our experiments. We then illustrate the quantitative findings of a large fault-injection simulation campaign on the fault-tolerant core and discuss the vulnerability comparison with previous representative fault-tolerant designs. The results show that the obtained resilience is comparable to a full triple modular redundancy at the cost of execution cycle count overhead instead of hardware overhead, yet with higher achievable clock frequency.INDEX TERMS Circuit faults, digital integrated circuits, fault detection, fault tolerant computing, field programmable gate arrays, microprocessors, multithreading, radiation hardening (electronics), redundancy, robustness.Open Access funding provided by 'Università degli Studi di Roma ''La Sapienza''' within the CRUI CARE Agreement

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Internet-of-Things end-nodes demand low power processing platforms characterized by heterogeneous dedicated units, controlled by a processor core running concurrent control threads. Such architecture scheme fits one of the main target application domain of the RISC-V instruction set. We present an open-source processing core compliant with RISC-V on the software side and with the popular Pulpino processor platform on the hardware side, while supporting interleaved multi-threading for IoT applications. The latter feature is a novel contribution in this application domain. We report details about the microarchitecture design along with performance data. This is the pre-print version of an article submitted to Lecture Notes on Electrical Engineering, Springer, in compliance with the Publisher's Selfarchiving Policy.