Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor

Cheikh, Abdallah; Sordillo, Stefano; Mastrandrea, Antonio; Menichelli, Francesco; Olivieri, Mauro

doi:10.1007/978-3-030-37277-4_62

Cited by 11 publications

(9 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The concept of the proposed work is to quantify the FT performance of the triple redundancy obtained by properly adapting an IMT core that supports three hardware threads. The open-source Klessydra-T [46] is an IMT processor core family based on a four-stage in-order pipeline that interleaves three or more hardware threads (Fig. 1).…”

Section: Microarchitecture Design a Baseline Microarchitecturementioning

confidence: 99%

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

et al. 2022

View full text Add to dashboard Cite

Fault management in digital chips is a crucial aspect of functional safety. Significant work has been done on gate and microarchitecture level triple modular redundancy, and on functional redundancy in multi-core and simultaneous-multi-threading processors, whereas little has been done to quantify the fault tolerance potential of interleaved-multi-threading. In this study, we apply the temporal-spatial triple modular redundancy concept to interleaved-multi-threading processors through a design solution that we call Buffered triple modular redundancy, using the soft-core Klessydra-T03 as the basis for our experiments. We then illustrate the quantitative findings of a large fault-injection simulation campaign on the fault-tolerant core and discuss the vulnerability comparison with previous representative fault-tolerant designs. The results show that the obtained resilience is comparable to a full triple modular redundancy at the cost of execution cycle count overhead instead of hardware overhead, yet with higher achievable clock frequency.INDEX TERMS Circuit faults, digital integrated circuits, fault detection, fault tolerant computing, field programmable gate arrays, microprocessors, multithreading, radiation hardening (electronics), redundancy, robustness.Open Access funding provided by 'Università degli Studi di Roma ''La Sapienza''' within the CRUI CARE Agreement

show abstract

Section: Microarchitecture Design a Baseline Microarchitecturementioning

confidence: 99%

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

et al. 2022

View full text Add to dashboard Cite

show abstract

“…Thread usage in a program significantly reduces the overhead involved in creating and managing threads, as well as sharing per-process state information. Since thread creation has lower overhead, it is focused on single-process multithreaded programs (Cheikh et al, 2020).…”

Section: Multithreaded Serversmentioning

confidence: 99%

Analysis of Multi-Threading and Cache Memory Latency Masking on Processor Performance Using Thread Synchronization Technique

Ehis

2023

Braz. J. of Sci.

View full text Add to dashboard Cite

Multithreading is a process in which a single processor executes multiple threads concurrently. This enables the processor to divide tasks into separate threads and run them simultaneously, thereby increasing the utilization of available system resources and enhancing performance. When multiple threads share an object and one or more of them modify it, unpredictable outcomes may occur. Threads that exhibit poor locality of memory reference, such as database applications, often experience delays while waiting for a response from the memory hierarchy. This observation suggests how to better manage pipeline contention. To assess the impact of memory latency on processor performance, a dual-core MT machine with four thread contexts per core is utilized. These specific benchmarks are chosen to allow the workload to include programs with both favorable and unfavorable cache locality. To eliminate the issue of wasting the wake-up signals, this work proposes an approach that involves storing all the wake-up calls. It asserts the wake-up calls to the consumer and the producer can store the wake-up call in a variable. An assigned value in working system (or kernel) storage that each process can check is a semaphore. Semaphore is a variable that reads, and update operations automatically in bit mode. It cannot be actualized in client mode since a race condition may persistently develop when two or more processors endeavor to induce to the variable at the same time. This study includes code to measure the time taken to execute both functions and plot the graph. It should be noted that sending multiple requests to a website simultaneously could trigger a flag, ultimately blocking access to the data. This necessitates some computation on the collected statistics. The execution time is reduced to one third when using threads compared to executing the functions sequentially. This exemplifies the power of multithreading.

show abstract

“…When the LSU fills the SPM banks with data from the 32-bit data memory port, a bank interleaver switches between the banks. The reader may refer to [5] for internal details of the units inside the MFU and SPMs. Furthermore, the coprocessor can be configured to implement the following different schemes of interaction with harts: Shared coprocessor: A single MFU/SPM subsystem is shared by all the harts.…”

Section: Hardware Acceleration Schemesmentioning

confidence: 99%

“…In these works, the architectural concept is a subset of those covered in our study. Our work builds on the activity reported in [5], that was an initial effort into designing a mathematical accelerator for a RISC-V core, and in [4], that addressed the best performing pipeline organization for an IMT RISC-V core.…”

mentioning

confidence: 99%

Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores

et al. 2021

Self Cite

View full text Add to dashboard Cite

Convolutional computation kernels are fundamental to today's edge computing applications. Interleaved-Multi-Threading (IMT) processor cores are an interesting approach to pursue the highest energy efficiency and lowest hardware cost in edge computing systems, yet they need hardware acceleration schemes to deal with heavy computational workloads like convolutional algorithms. Following a vector approach to accelerate convolutions, this study explores possible alternatives to implement vector coprocessing units in IMT cores, showing the application-dependence of the optimal balance among the hardware architecture parameters.

show abstract

Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor

Cited by 11 publications

References 3 publications

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

Analysis of Multi-Threading and Cache Memory Latency Masking on Processor Performance Using Thread Synchronization Technique

Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores

Contact Info

Product

Resources

About