Dual damascene BEOL processing using multilevel step and flash imprint lithography

Abstract

Step and Flash Imprint Lithography (S-FIL ® ) in conjunction with Sacrificial Imprint Materials (SIM) shows promise as a cost effective solution to patterning sub 45 nm features and is capable of simultaneously patterning two levels of interconnect structures, which provides a high throughput and low cost BEOL process. This paper describes the integration of S-FIL into an industry standard Cu/low-k dual damascene process that is being practiced in the ATDF at Sematech in Austin. The pattern transferring reactive ion etching (RIE) process is the most critical step and was extensively explored in this study. In addition to successful process development, the results provide useful insight into the optimal design of multilevel templates which must take into account the characteristics of both the imaging material and the dielectric layer.The template used in this study incorporates both the via and trench levels of an M2 (Metal 2) test vehicle that incorporates via chains with varying via dimensions, Kelvin test structures, serpentines, etc. The smallest vias on the template are 120 nm vias with an aspect ratio of 2.0 and the smallest dense lines are 125 nm/175 nm with an aspect ratio of 2.9. Two inter-level dielectrics (ILD), Coral ® and Black Diamond ® were studied. No trench etch stop was incorporated in the ILD film stack. A multi-step, in-situ etching scheme was developed that achieves faithful pattern transfer from the sacrificial imprint material (SIM) into the underlying low k ILD with surprisingly wide process latitude. This multi-step scheme includes the following etch steps: a residual layer open, a via etch, a trench descum, a trench etch, and an SIM removal ash. Among these steps, the trench etch was found to be the most challenging to develop and it holds the key to producing high aspect ratio dual damascene features. An etching chemistry based on two fluorocarbon gases, CF 4 and C 4 F 8 , was found to be very effective in delivering the desired etch profiles with optimal sidewall angle, minimal facet formation. The optimized etch process can be exploited to provide substantial size reduction and/or increased aspect ratio relative to the template. In this way structures with final critical dimensions of 95 nm in vias with aspect ratio of 3.0 and 67 nm/233 nm in dense lines with aspect ratio of 3.6 were demonstrated with wide process latitude. This enables manufacturing of the template at larger dimensions, which simplifies both fabrication and inspection.The successful development of the dual damascene RIE process at the second metal (M2) level was demonstrated in a mixed and matched build with an ATDF standard first layer metal (M1) process. The M1 dielectric was TEOS and was patterned by 248 nm lithography. The M2 and Via levels used Coral as ILD and both levels were patterned simultaneously by S-FIL using Molecular Imprint Imprio 55 and Imprio 100 imprint tools. This electrical test vehicle provided solid evidence that S-FIL is fully compatible with industry standard dual damascene process.

Fabrication of self-aligned multilevel nanostructures

“…The structure illustrated in Fig. 6is a symmetric multilevel geometry, similar to that used in the dual damascene work for copper interconnects [16][17]27]. A selfaligned technique to fabricate such shapes is used to validate the techniques developed in this research.…”

“…In this regard, nanoimprint lithography [20] - [24] has been demonstrated as a high throughput, low-cost lithographic technique capable of patterning arbitrary geometries with demonstrated sub-10 nm feature resolution. Moreover, multilevel imprint lithography has been demonstrated to pattern multilevel structures with high-fidelity by replicating an existing multilevel pattern on the template [25][26][27][28]. Since the multilevel pattern is pre-coded in the template geometry, multilevel imprint lithography can lend itself to faithful and cost-effective replication of the same geometry without needing further alignment or overlay.…”

Open/short-TEG evaluation of 24nm-half-pitch-W damascene interconnects based on nanoimprint lithography

“…The BEOL layers, which mediate between the transistors and the package interconnects, consist of more than 10 layers of metal interconnects and vias 10 . Because NIL can transfer entire multilevel structures simultaneously, the wiring layers and via layers can be patterned in a single process, which may contribute to significant cost reduction in BEOL processing [11][12][13] . In addition, during a demonstration of a 70-nm-half-pitch single damascene process 14 , it was clarified that NIL provides excellent performance in terms of its flexible layout patterning capability and the dimensional controllability of the interconnect linewidths without the need for optical proximity correction (OPC) 15 , in contrast to ArF immersion lithography.…”

Fabrication of Copper Damascene Patterns on Polyimide Using Direct Metallization on Trench Templates Generated by Imprint Lithography

“…The microfabrication of electronic components with high resolution onto various substrates has attracted much attention in the manufacturing processes of electronic, optical, and mechanical devices. − Recently, a damascene process is mainly used to fabricate an ultrahigh-density copper wiring in the semiconductor industry, which involves fabrication of trench structures on the substrates using reactive ion etching (RIE) and metal deposition in trench patterns followed by removal of the superfluous copper film with a chemical mechanical polishing (CMP). − The copper minute wiring obtained by conventional damascene approaches shows line width in the range of nanometers and is embedded into dielectric rigid substrate such as silicon dioxide, and thus, this structure provides an effective interconnection with high adhesion. − This approach, although being widely employed for the practical fabrication of damascene structure using rigid substrate, − was not utilized for the fabrication of metal damascene on flexible substrates. Thus, the development of new methodologies for fabrication of damascene structures using flexible polymer substrates is crucial for the flexible printed circuit (FPC) fabrication, multichip module (MCM) packaging, magnetic data storage, and ultralarge-scale integrated (ULSI) circuit technology with high performance.…”