Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks

Esmaeili, Seyed A.; Al-Khalili, A.J.; Cowan, Glenn

doi:10.1049/iet-cdt.2010.0005

Cited by 15 publications

(10 citation statements)

References 10 publications

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“…The clock distribution networks synchronise the flow of data among the synchronous data paths. The design of these networks can considerably affect the system-wide performance and the reliability [25][26][27]. For the analysis of the proposed design, a hierarchical clock tree with the balanced paths along the interconnect lines to each of the leaf cell is chosen for an optimised delay and a minimum skew.…”

Section: Clock Distribution Network With the H-clock Tree And 102leafmentioning

confidence: 99%

Self‐gated resonant‐clocked flip‐flop optimised for power efficiency and signal integrity

Jawahar

Murthy

Bhaaskaran

2016

IET Circuits, Devices & Systems

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The clock distribution network primarily comprises of the clock tree and the flip-flops. The resonant clocking, which drives a clock tree possesses a large potential for a sweeping power minimisation in the clock network. In addition, the clocked flip-flops, being the crucial timing elements, have become a major contributor to the total power dissipation. Thus, this study proposes a novel 'self-gated resonant (SGR) clocked flip-flop' to address these concerns. The proposed flip-flop achieves reduced dynamic power dissipation, in addition to the negative setup time, which makes the design more tolerant to the clock skew. This feature also reduces the D-Q delay, thus improving the timing performance of the flip-flop. Second, this study investigates the use of the resonant clock in a hierarchical clock tree distribution network operating 1024 flip-flops at its leaf nodes. The advantages of the SGR clocked flip-flop are validated through exhaustive simulations and comparisons, with the flip-flop structures available in the literature. Furthermore, the post-layout simulations of a typical H-clock tree driving the 1024 flip-flops at the leaf cells have been carried out. Cadence ® EDA tools and the 45 nm process technology files have been used to substantiate the merits of the proposed design.

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Section: Clock Distribution Network With the H-clock Tree And 102leafmentioning

confidence: 99%

Self‐gated resonant‐clocked flip‐flop optimised for power efficiency and signal integrity

Jawahar

Murthy

Bhaaskaran

2016

IET Circuits, Devices & Systems

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“…The energy recovery clocking scheme is very attractive as a way to address this concern. Unlike the traditional square-wave clocking scheme (see Figure 1(a)) [8], the resonant clocking scheme uses an on-chip inductor, an input decoupling capacitor with the capacitance of the clock distribution network, to generate a sinusoidal clock (see Figure 1(b)) [27,9,26,3]. The energy recovery scheme achieves low energy dissipation by restricting current from flowing across devices with low voltage drop, enabling significant power saving.…”

Section: Introductionmentioning

confidence: 99%

“…The importance of designing low-power and high-performance timing elements has led to the design of different kinds of low-power latches and FFs in the literature [8,21,30,19,15,32,7,22,29,28,11,20]. A number of papers have proposed new styles of latches and FFs that improve power, speed, and energy or demonstrate special characteristics of timing and soft error robustness.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops

Islam

2018

J Electron Test

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An energy recovery or resonant clocking scheme is very attractive for saving the clock power in nanoscale ASICs and systems-on-chips, which have increased functionality and larger die sizes. The technology scaling followed Moore's law, that lowers node capacitance and supply voltage, making nanoscale integrated circuits more vulnerable to radiation-induced single event upsets (SEUs) or soft errors. In this work, we propose soft-error robust flipflops (FFs) capable of working with a sinusoidal resonant clock to save the overall chip power. The proposed conditional-pass Quatro (CPQ) FF and true single phase clock energy recovery (TSPCER) FF are based on a unique soft error robust latch, which we refer to as a Quatro latch. The proposed C 2 -DICE FF is based on a dual interlocked cell (DICE) latch. In addition to the storage cell, each FF consists of a unique input-stage and a two-transistor, two-input output buffer. In each FF with a sinusoidal clock, the transfer unit passes the data to the Quatro and DICE latches. The latches store the data values at two storage nodes and two redundant nodes, the latter enabling recovery from a particle-induced transient with or without multiple-node charge sharing. Postlayout simulations in 65nm CMOS technology show that the FF exhibits as much as 82% lower power-delay product compared to recently reported soft error robust FFs. We implemented 1024 proposed FFs distributed in an H-tree clock network driven by a resonant clock-generator that generates a 1-5 GHz sinusoidal clock signal. The simulation results show a power reduction of 93% on the clock tree and total power saving of up to 74% as compared to the same implementation using the conventional square-wave clocking scheme and FFs.

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“…The sense-ampli¯er based°ip-°op (SAFF) also appeared to be a good candidate for designing the high performance digital circuit. [9][10][11][12][13][14][15] In order to design energy-e±cient and high performance SAFFs, we apply the sinusoidal energy recovery clocking to SAFFs. Single-phase sinusoidal power-clock approach provides advantages over square or ramp energy recovering clock approach such as simple clock generation and distribution, single inductor tuning, energy-e±ciency and low transistor count.…”

Section: Introductionmentioning

confidence: 99%

Sinusoidal Clocked Sense-Amplifier-Based Energy Recovery Flip-Flops

Kanungo

Dasgupta

2014

J CIRCUIT SYST COMP

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Energy recovery clocking is an ultimate solution to the ultra low power sequential digital circuit design. In this paper, we present a new slave latch for a sense-ampli¯er based°ip-°op (SAFF). Energy recovery sinusoidal clock is applied to the low power SAFF. Extensive simulation based comparisons among reported and proposed SAFF are carried-out at 90 nm CMOS technology node. The proposed°ip-°op operating with energy recovery single phase sinusoidal clock shows better performance. The proposed°ip-°op also reduces the leakage current and glitch.

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Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks

Cited by 15 publications

References 10 publications

Self‐gated resonant‐clocked flip‐flop optimised for power efficiency and signal integrity

Self‐gated resonant‐clocked flip‐flop optimised for power efficiency and signal integrity

Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops

Sinusoidal Clocked Sense-Amplifier-Based Energy Recovery Flip-Flops

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