Dual loop cascode‐Miller compensation with damping factor control unit for three‐stage amplifiers driving ultralarge load capacitors

Abstract

An area-efficient amplifier topology is presented for three-stage amplifiers driving ultralarge load capacitor with reduced power consumption. It contains two high-speed ac feedback loops made from embedded current buffers and smallsize compensation capacitors, which pushes the nondominant complex poles to very high frequencies. To further improve the stability, a local impedance damping block is embedded. At the higher frequencies, it suppresses the high resistive property at the second-stage output, thereby increasing the damping factor of the complex poles and improving the overall gain margin. For identical bandwidth, the overall silicon area of the on-chip compensation capacitor is therefore decreased, leading to enhanced small-signal and large-signal performance metrics. Coined dual loop cascode-Miller compensation with damping factor control unit, the effectiveness of the proposed approach is investigated through simulation results in 90-nm complementary metal-oxide-semiconductor (CMOS) technology. An implementation based on the proposed technique consumes a quiescent current of 17 μA from a 1.2 V voltage supply. For a load capacitance equal to 560 pF, it achieves a gain-bandwidth frequency of 4.34 MHz, an average slew-rate of 1.72 V/μs, and an average settling time of 0.52 μs, when the overall compensation capacitance is set to 1.55 pF. The proposed design can supply the load capacitors up to 35 nF.

Systematic circuit design and analysis using generalised g m / I D functions of MOS devices

“…This approach is re-iterated for all outputs, and for other process and temperature corners once demanded. Several methodologies have been proposed to design the analogue circuits based on devices transconductances and bias currents [30][31][32][33][34][35][36]. We, therefore, present in Fig.…”

“…Several methodologies have been proposed to design the analogue circuits based on devices transconductances and bias currents [30–36]. We, therefore, present in Fig.…”

Global impedance attenuation network for multistage OTAs driving a broad range of load capacitor

“…High‐gain multistage amplifiers are preferred over single‐stage configurations in modern mixed‐signal processing modules with stringent accuracy requirement . These amplifiers ensure that maximum signal dynamic range is achieved under the low‐voltage supply of short‐channel metal‐oxide semiconductor (MOS) transistors since the output stage can be implemented by two transistors only.…”

Hybrid cascode compensation with Q-factor control module for three-stage OTAs driving ultra-large load capacitors

“…Still, the high Q-factor limits the OTA performance for the small load capacitors. Dual loop cascode Miller compensation with damping factor control unit (DLCDFC) (Aminzadeh and Dashti, 2018) and cascode global impedance attenuation (CGIA) (Aminzadeh et al, 2020) modify the high Q-factor of the HCFC amplifier using a serial RC network at the output of the second stage or both first and second stages, respectively. Significant silicon area is however, occupied by the required resistance and capacitance of hundreds kX and several hundreds fF.…”