Introduction: The use of laparoscopic management as a first choice for the treatment of duodenal perforation is gaining ground but is not routine in many centers. In this report, we aim to report our experience with laparoscopy as the first approach for the repair of duodenal perforation. Materials and Methods: This is a retrospective review of patients during our initial experience with the use of laparoscopy for the treatment of duodenal perforation between 2009 and 2013. Results: A total of 100 patients underwent management of duodenal perforation. Laparoscopy was attempted initially in 76 patients (76%) and completed in 64 patients (64%). The length of hospital stay was shorter in the laparoscopic group (mean 2.6) than in the open group (mean 3.1) (p = 0.008). Complications developed in 14 patients (20%). There was a tendency towards fewer admissions to intensive care, less acute kidney injuries, and less acute respiratory distress syndrome in the laparoscopic group. In patients who underwent laparoscopic surgery, the chances of uneventful recovery were 4.3 times higher than in those patients who underwent open surgery (95% CI 1.3–13.5, p = 0.014). Conclusions: Laparoscopy in the treatment of perforated duodenal ulcer is safe and can be utilized as a routine approach for the treatment of this pathology.

An area-efficient amplifier topology is presented for three-stage amplifiers driving ultralarge load capacitor with reduced power consumption. It contains two high-speed ac feedback loops made from embedded current buffers and smallsize compensation capacitors, which pushes the nondominant complex poles to very high frequencies. To further improve the stability, a local impedance damping block is embedded. At the higher frequencies, it suppresses the high resistive property at the second-stage output, thereby increasing the damping factor of the complex poles and improving the overall gain margin. For identical bandwidth, the overall silicon area of the on-chip compensation capacitor is therefore decreased, leading to enhanced small-signal and large-signal performance metrics. Coined dual loop cascode-Miller compensation with damping factor control unit, the effectiveness of the proposed approach is investigated through simulation results in 90-nm complementary metal-oxide-semiconductor (CMOS) technology. An implementation based on the proposed technique consumes a quiescent current of 17 μA from a 1.2 V voltage supply. For a load capacitance equal to 560 pF, it achieves a gain-bandwidth frequency of 4.34 MHz, an average slew-rate of 1.72 V/μs, and an average settling time of 0.52 μs, when the overall compensation capacitance is set to 1.55 pF. The proposed design can supply the load capacitors up to 35 nF.

In this paper, a refractive index plasmonic sensor including a waveguide of metal-insulatormetal with side coupled octagonal cavity ring has been suggested. The sensory and transmission feature of the structure has been analyzed numerically using Finite Element Method numerical solution. The effect of coupling distance and changing the width of metal-insulator-metal waveguide and refractive index of the dielectric located inside octagonal cavity-which are the effective factors in determining the sensory feature-have been examined so completely that the results of the numerical simulation show a linear relation between the resonance wavelength and refractive index of the liquid/gas dielectric material inside the octagonal cavity ring. High sensitivity of the sensor in the resonance wavelength, simplicity and a compact geometry are the advantages of the refractive plasmonic sensor advised which make that possible to use it for designing high performance nano-sensor and bio-sensing devices.

Room-temperature analog-to-digital converters (ADCs) based on nanoscale silicon (Si) quantum dot (QD)-based single-electron transistors (SETs) can be very attractive for high-speed processors embedded in future generation nanosystems. This paper focuses on the design and modeling of advanced single-electron converters suited for operation at room temperature. In contrast to conventional SETs with metallic QD, the use of sub-10-nm Si QD results in stable operation at room temperature, as the observable Coulomb blockade regime covers effectively the higher temperature range. Si QD-based SETs are also fully compatible with advanced CMOS technology and they can be manufactured using routine nanofabrication steps. At first, we present the principles of operation of Si SETs used for room-temperature operation. Possible flash-type ADC architectures are then investigated and the design considerations of possible Coulomb oscillation regimes are addressed. A modified design procedure is then introduced for [Formula: see text]-bit SET-based ADCs, and validated through simulation of a 3-bit ADC with a sampling frequency of 5 GS/s. The ADC core is comprised from a capacitive signal divider followed by three periodic symmetric functions (PSFs). Simulation results demonstrate the stability of output signals at the room-temperature range.

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