Dual-Material Gate Approach to Suppression of Random-Dopant-Induced Characteristic Fluctuation in 16 nm Metal–Oxide–Semiconductor Field-Effect-Transistor Devices

Li, Yiming; Lee, Kuo-Fu; Yiu, Chun-Yen; Chiu, Yu–Jen; Chang, Ru-Wei

doi:10.7567/jjap.50.04dc07

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Device Structure and Simulation1

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Cited by 3 publications

(1 citation statement)

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“…The simulation is drift-diffusion based without impact ionization, and the mobility model includes the effects of doping concentration and electric field. The density gradient model applied in [20,26,27] is utilized to account for the quantum effects. Band-gap narrowing (BGN) due to high doping is modeled using Old Slotboom BGN model.…”

Section: Device Structure and Simulationmentioning

confidence: 99%

Improved performance of nanoscale junctionless transistor based on gate engineering approach

Wang

Shan

Dou

et al. 2015

Microelectronics Reliability

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Section: Device Structure and Simulationmentioning

confidence: 99%

Improved performance of nanoscale junctionless transistor based on gate engineering approach

Wang

Shan

Dou

et al. 2015

Microelectronics Reliability

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Source/Drain Series Resistance Extraction in HKMG Multifin Bulk FinFET Devices

2015

IEEE Trans. Semicond. Manufact.

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Effective extraction of source/drain (S/D) series resistances is a challenging task owing to poor epi-growth and non-uniform distribution of current density in S/D, critical limitation of restrictive design rule, ultra-thin contact film, and complicated 3D FinFET structure. In this paper, we report a test structure for measurement of linear and non-linear S/D series resistances. This technique enables us to evaluate each component of S/D series resistances resulting from the S/D contact, the S/D epi-growth fin, the S/D extension, and the channel gate, respectively. The S/D series resistance for fins on different layout location of the same diffusion is characterized and modeled by connection with a specified S/D contact on it. Furthermore, the S/D series resistance of each fin can be analytically calculated, respectively, by swapping the S/D bias condition. The proposed test structure and extraction technique provides a robust monitoring tool to diagnose a process weak point of the 16-nm multi-fin high-κ/metal gate bulk FinFET devices.

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A Systematic Approach to Correlation Analysis of In-Line Process Parameters for Process Variation Effect on Electrical Characteristic of 16-nm HKMG Bulk FinFET Devices

2016

IEEE Trans. Semicond. Manufact.

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Dual-Material Gate Approach to Suppression of Random-Dopant-Induced Characteristic Fluctuation in 16 nm Metal–Oxide–Semiconductor Field-Effect-Transistor Devices

Cited by 3 publications

References 32 publications

Improved performance of nanoscale junctionless transistor based on gate engineering approach

Improved performance of nanoscale junctionless transistor based on gate engineering approach

Source/Drain Series Resistance Extraction in HKMG Multifin Bulk FinFET Devices

A Systematic Approach to Correlation Analysis of In-Line Process Parameters for Process Variation Effect on Electrical Characteristic of 16-nm HKMG Bulk FinFET Devices

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