Dual Material Pile Gate Approach for Low Leakage Finfet

Abstract

FinFET (Fin Field-Effect Transistor) technology has recently seen a major increase in adoption for use in integrated circuits because of its high immunity to short channel effects and its further ability to scale down. Previously, a major research contribution was made to reduce the leakage current in the conventional bulk devices. So many different alternatives like bulk isolation and oxide isolation are all having some pros and cons. Here in this paper, we present a novel pile gate FinFET structure to reduce the leakage current, as compared with Bulk FinFET without using any pstop implant or isolation oxide as in the Silicon-on-Insulator (SOI). The major advantage of this type of structure is that there is no need of high substrate doping, a 100% reduction in the random dopant fluctuation (RDF) and an increase in the I ON /I OFF value. It can be very useful to improve the drain-induced barrier lowering (DIBL) at smaller technological nodes. All the work is supported by 3D TCAD simulations, using Cogenda TCAD.

Performance Parameter Evaluation of 7nm FinFET by Tuning Metal Work Function and High K Dielectrics

“…As a result of these the leakage current and short channel effects increasing. (Chopade & Padole, 2017a) A metal gate technology can overcome these issues by providing the appropriate gate work functions. Work function is the minimum energy (usually measured in electron volts) needed to remove an electron from a solid to a point immediately outside the solid surface.…”

“…So, in this work, the effect by changing the high-k gate dielectrics & metal work function observe on the device. The Fin-FET device is modelled by fluctuating the low dielectric material with high k dielectrics and observe the effect on the performance of leakage current, DIBL (Chopade & Padole, 2017a;Ranka & Rana, 2011). The leakage current has an essential helping of power consumption.…”