2017
DOI: 10.1109/tcsi.2016.2615084
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Dual-Mode All-Digital Baseband Receiver With a Feed-Forward and Shared-Memory Architecture for Dual-Standard Over 60 GHz NLOS Channel

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Cited by 24 publications
(21 citation statements)
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“…7a. We implement a configurable packet detector using a normalized auto-correlation algorithm [11,14] which detects the periodic sequences used for packet preambles [31,33]. The block is flexible to be used with different preambles with different periods of repetitive sequences, and different SSR factors for different sampling frequencies.…”
Section: Receiver Blocksmentioning
confidence: 99%
“…7a. We implement a configurable packet detector using a normalized auto-correlation algorithm [11,14] which detects the periodic sequences used for packet preambles [31,33]. The block is flexible to be used with different preambles with different periods of repetitive sequences, and different SSR factors for different sampling frequencies.…”
Section: Receiver Blocksmentioning
confidence: 99%
“…For reliable system operation these two effects have to be compensated. The CPE is typically estimated per OFDM symbol using pilot subcarriers known to receiver and corrected by de-rotation in frequency domain of all the subcarriers by the estimated phase error and has relatively simple implementation, [3], [12]- [23]. The estimation and compensation of the PN induced ICI is much more complex and in some cases is impractical for implementation in the high data rate hardware architecture used in the IEEE 802.11ay system.…”
Section: Introductionmentioning
confidence: 99%
“…Therefore, the baseband hardware architecture has high parallelization factor and typically demodulates 8 or 16 subcarriers per clock. Beyond that, there is a strict requirement on the processing delay per hardware block, typically estimated equal to ~100 ns, which makes the implementation of the complicated PN ICI compensation algorithms impractical, [21]- [23].…”
Section: Introductionmentioning
confidence: 99%
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