No abstract

This paper deals with direction of arrival (DOA) estimation and blind signal separation (BSS) based on independent component analysis (ICA) with robust capabilities. An efficient demixing procedure of complex-valued ICA is presented here, which combines the signal-subspace demixing procedure exploiting individual signal-subspace projection and Newton's iteration algorithm based on maximization of the approximate negentropy of non-Gaussian signal for array signal processing. It resolves the problems of order ambiguity and identifiability of traditional ICA for time-domain BSS. The proposed method could be directly applied to radar, sonar, radio surveillance, and communications systems for separating signals and estimating relative DOAs of signals. Several computer simulation examples for perturbations to the array manifold, unknown noise environments, and Rayleigh fading channel are provided to illustrate the effectiveness of the proposed method.

No abstract

In this article, a modified complex-valued FastICA algorithm is utilized to extract the specific feature of the Gaussian noise component from mixtures so that the estimated component is as independent as possible to the other non-Gaussian signal components. Once the noise basis vector is obtained, we can estimate direction of arrival by searching the array manifold for direction vectors, which are as orthogonal as possible to the estimated noise basis vector especially for highly correlated signals with closely spaced direction. Superior resolution capabilities achieved with the proposed method in comparison with the conventional multiple signal classification (MUSIC) method, the spatial smoothing MUSIC method, and the signal subspace scaled MUSIC method are shown by simulation results.

A multimedia system-on-a-chip (SoC) usually contains one or more programmable digital signal processors (DSP) to accelerate data-intensive computations. But most of these DSP cores are designed originally for standalone applications, and they must have some overlapped (and redundant) components with the host microprocessor. This paper presents a compact DSP for multi-core systems, which is fully programmable and has been optimized to execute a set of signal processing kernels very efficiently. The DSP core was designed concurrently with its automatic software generator based on high-level synthesis. Moreover, it performs lightweight arithmetic-the static floating-point (SFP), which approximates the quality of floating-point (FP) operations with the hardware similar to that of the integer arithmetic. In our simulations, the compact DSP and its auto-generated software can achieve 3X performance (estimated in cycles) of those DSP cores in the dualcore baseband processors with similar computing resources. Besides, the 16-bit SFP has above 40 dB signal to round-off noise ratio over the IEEE single-precision FP, and it even outperforms the hand-optimized programs based on the 32-bit integer arithmetic. The 24-bit SFP has above 64 dB quality, of which the maximum precision is identical to that of the single-precision FP. Finally, the DSP core has been implemented and fabricated in the UMC 0.18µm 1P6M CMOS technology. It can operate at 314.5 MHz while consuming 52mW average power. The core size is only 1.5 mm×1.5 mm including the 16 KB on-chip memory and the AMBA AHB interface.