Dual-Mode Electrical-Optical Flip-Chip I/O Interconnects and a Compatible Probe Substrate for Wafer-Level Testing

Bakir, Muhannad S.; Dang, Bing; Thacker, Hiren; Ogunsola, O.O.; Ogra, R.; Meindl, J.D.

doi:10.1109/ectc.2006.1645744

Cited by 3 publications

(1 citation statement)

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“…In this approach, polymer pins are each used to provide two (dual) interconnect functions between the chip and package substrate. Sidewall metallized optical and fluidic pins are used to provide electrical-optical [19] and electricalfluidic interconnections, respectively. SEM images of such I/0 interconnects are shown in Figure 5 and Figure 6.…”

Section: Trimodal I/o Interconnect Configurationsmentioning

confidence: 99%

‘trimoda’ Wafer-Level Package: Fully Compatible Electrical, Optical, and Fluidic Chip I/O Interconnects

Bakir

Dang

Ogunsola

et al. 2007

2007 Proceedings 57th Electronic Components and Technology Conference

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We describe the fabrication, assembly, and testing of a wafer-level package with fully compatible electrical, optical, and fluidic ('trimodal') chip I/0 interconnects. Various trimodal interconnect configurations are introduced. The trimodal I/Os are fabricated using five minimally demanding masking steps. In order to experimentally characterize the trimodal I/Os, we fabricate two separate substrates to test the chips with these I/Os in a piecewise manner. In the first assembly demonstration, we perform electrical and optical I/0 interconnection measurements. In the second assembly demonstration, we perform electrical and fluidic interconnection measurements. Measurements reveal that the metal-clad optical pins (55xl 10 pm in size) attenuate an optical signal (632.8 nm wavelength) by 3.6 %. The electrical resistance is measured to be 50 mQ. It is also shown that the fluidic I/Os with the integrated back-side thermofluidic microchannel heat sink can achieve thermal resistance as low as 0.17 oC_cm2/W. Cooling of localized power density of >300 W/cm2 is also demonstrated. Mechanical testing of polymer pins before and after metallization is also reported. I. IntroductionThe performance and cost of silicon ancillary technologies have not scaled in the same way that silicon technology has. Historically, shrinking of the minimum feature sizes of a transistor have led to increased switching speed, lowered energy dissipation per switching operation, and decreased cost per transistor. These results are the basis of Moore's Law, which asserts that the transistor density in a chip doubles every 18 months. Remarkably, Moore's Law has accurately projected the integration trend of integrated circuits (ICs) for more than 40 years. Today, billion-plus transistor multiprocessors are available on the market.However, while silicon technology has continued to progress at a very rapid pace, silicon ancillary technologies have scaled in reverse. The inabilities to remove heat, provide high-bandwidth off-chip interconnects, and efficiently deliver power to a gigascale system have imposed significant constraints on system performance. According to the International Technology Roadmap for Semiconductors (ITRS) [1], the projected junction-to-ambient thermal resistance will be less than 0.2°C/W by the end of the roadmap. Moreover, it is projected that high-performance chips will drain more than 280 A at 0.7 V. With respect to signaling, it is projected that off-chip communication frequency will be greater than 80 GHz (for a small number of I/Os). Meeting the heat removal, power delivery, and off-chip signaling requirements simultaneously motivates the need to explore disruptive new silicon ancillary technologies.

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Section: Trimodal I/o Interconnect Configurationsmentioning

confidence: 99%