Dual-Port Content Addressable Memory for Cache Memory Applications

Abumwais, Allam; Amirjanov, Adil; Uyar, Kaan; Eleyat, Mujahed

doi:10.32604/cmc.2022.020529

Cited by 3 publications

(9 citation statements)

References 23 publications

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“…The previous article [7] findings support incorporating DPCAM as tiny shared cache memory inside multi-core CPUs to improve performance. Many related works improve the shared level of caches in multi-core systems.…”

Section: Related Workmentioning

confidence: 53%

“…By coming up with a new design that addresses the multi-core systems that address the issue of gaping memory speed and processor, there is a fundamental aspect of solving the issue of our research on shared cache based on content-addressable memory in a multicore architecture. Abumwais contributes to the discussion by proposing that DPCAM is a novel architecture for a specialized pipeline cache memory for multi-core CPUs that are being shown DPCAM [7]. Also included a novel replacement algorithm based on hardware, referred to as an NFRA, which is intended to lower the cost inefficiency of the cache controller while simultaneously improving the delay of cache accesses.…”

Section: Related Workmentioning

confidence: 99%

“…To the best of our knowledge, DPCAM that was proposed in [7] is the first work that addresses using the content addressable memory as a shared cache and taking advantage of its features. Fig.…”

Section: Dpcam Architecturementioning

confidence: 99%

“…In the proposed DPCAM, a NFRA replacement algorithm and a new writing mechanism were presented in [7]. The write operation is based on a pointer is implemented in the CU.…”

Section: A Modified Replacement Policy For Dpcammentioning

confidence: 99%

“…In the previous work [7] a special purpose shared memory architecture based on CAM called DPCAM was presented. In addition, an efficient replacement algorithm, called NFRA, which is based on hardware rather than software executed by the cache controller was also presented.…”

Section: Introductionmentioning

confidence: 99%

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Shared Cache Based on Content Addressable Memory in a Multi-Core Architecture

Abumwais¹,

Obaid²

2023

Computers, Materials &Amp; Continua

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Modern shared-memory multi-core processors typically have shared Level 2 (L2) or Level 3 (L3) caches. Cache bottlenecks and replacement strategies are the main problems of such architectures, where multiple cores try to access the shared cache simultaneously. The main problem in improving memory performance is the shared cache architecture and cache replacement. This paper documents the implementation of a Dual-Port Content Addressable Memory (DPCAM) and a modified Near-Far Access Replacement Algorithm (NFRA), which was previously proposed as a shared L2 cache layer in a multi-core processor. Standard Performance Evaluation Corporation (SPEC) Central Processing Unit (CPU) 2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache layer. Results show improved performance of the multicore processor's DPCAM and NFRA algorithms, corresponding to a higher number of concurrent accesses to shared memory. The new architecture significantly increases system throughput and records performance improvements of up to 8.7% on various types of SPEC 2006 benchmarks. The miss rate is also improved by about 13%, with some exceptions in the sphinx3 and bzip2 benchmarks. These results could open a new window for solving the long-standing problems with shared cache in multi-core processors.

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Section: Related Workmentioning

confidence: 53%

Section: Related Workmentioning

confidence: 99%

Section: Dpcam Architecturementioning

confidence: 99%

“…In the proposed DPCAM, a NFRA replacement algorithm and a new writing mechanism were presented in [7]. The write operation is based on a pointer is implemented in the CU.…”

Section: A Modified Replacement Policy For Dpcammentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Shared Cache Based on Content Addressable Memory in a Multi-Core Architecture

Abumwais¹,

Obaid²

2023

Computers, Materials &Amp; Continua

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A Scalable Interconnection Scheme in Many-Core Systems

Abumwais,

Eleyat

2023

CMC

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Recent architectures of multi-core systems may have a relatively large number of cores that typically ranges from tens to hundreds; therefore called many-core systems. Such systems require an efficient interconnection network that tries to address two major problems. First, the overhead of power and area cost and its effect on scalability. Second, high access latency is caused by multiple cores' simultaneous accesses of the same shared module. This paper presents an interconnection scheme called N-conjugate Shuffle Clusters (NCSC) based on multi-core multicluster architecture to reduce the overhead of the just mentioned problems. NCSC eliminated the need for router devices and their complexity and hence reduced the power and area costs. It also resigned and distributed the shared caches across the interconnection network to increase the ability for simultaneous access and hence reduce the access latency. For intra-cluster communication, Multi-port Content Addressable Memory (MPCAM) is used. The experimental results using four clusters and four cores each indicated that the average access latency for a write process is 1.14785 ± 0.04532 ns which is nearly equal to the latency of a write operation in MPCAM. Moreover, it was demonstrated that the average read latency within a cluster is 1.26226 ± 0.090591 ns and around 1.92738 ± 0.139588 ns for read access between cores from different clusters.

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New Content Addressable Memory Architecture for Multi-Core Applications

Abumwais,

Obaid

2024

Computer Memory and Data Storage

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The future of massively parallel computation appears promising due to the emergence of multi- and many-core computers. However, major progress is still needed in terms of the shared memory multi- and many-core systems, specifically in the shared cache memory architecture and interconnection network. When multiple cores try to access the same shared module in the shared cache memory, issues arise. Cache replacement methods and developments in cache architecture have been explored as solutions to this. This chapter introduces the Near-Far Access Replacement Algorithm (NFRA), a new hardware-based replacement technique, as well as a novel dedicated pipeline cache memory design for multi-core processors, known as dual-port content addressable memory (DPCAM). The experiments show that the access latency for write/read operations of a DPCAM is lower than that of a set-associative (SA) cache memory, with the latency of a write operation staying the same regardless of the size of the DPCAM. It is estimated that the power usage will be 7% greater than a SA cache memory of the same size.

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Dual-Port Content Addressable Memory for Cache Memory Applications

Cited by 3 publications

References 23 publications

Shared Cache Based on Content Addressable Memory in a Multi-Core Architecture

Shared Cache Based on Content Addressable Memory in a Multi-Core Architecture

A Scalable Interconnection Scheme in Many-Core Systems

New Content Addressable Memory Architecture for Multi-Core Applications

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