Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed. This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory (DPCAM). In addition, it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm (NFRA) to reduce the cost overhead of the cache controller and improve the cache access latency. The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory. Moreover, it was shown that a latency of a read operation is nearly constant regardless of the size of DPCAM. However, an estimation of the power dissipation showed that DPCAM consumes about 7% greater than a set-associative cache memory of the same size. These results encourage for embedding DPCAM within the multicore processors as a small shared cache memory.

Modern shared-memory multi-core processors typically have shared Level 2 (L2) or Level 3 (L3) caches. Cache bottlenecks and replacement strategies are the main problems of such architectures, where multiple cores try to access the shared cache simultaneously. The main problem in improving memory performance is the shared cache architecture and cache replacement. This paper documents the implementation of a Dual-Port Content Addressable Memory (DPCAM) and a modified Near-Far Access Replacement Algorithm (NFRA), which was previously proposed as a shared L2 cache layer in a multi-core processor. Standard Performance Evaluation Corporation (SPEC) Central Processing Unit (CPU) 2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache layer. Results show improved performance of the multicore processor's DPCAM and NFRA algorithms, corresponding to a higher number of concurrent accesses to shared memory. The new architecture significantly increases system throughput and records performance improvements of up to 8.7% on various types of SPEC 2006 benchmarks. The miss rate is also improved by about 13%, with some exceptions in the sphinx3 and bzip2 benchmarks. These results could open a new window for solving the long-standing problems with shared cache in multi-core processors.

Renewable energy is a safe and limitless energy source that can be utilized for heating, cooling, and other purposes. Wind energy is one of the most important renewable energy sources. Power fluctuation of wind turbines occurs due to variation of wind velocity. A wind cube is used to decrease power fluctuation and increase the wind turbine's power. The optimum design for a wind cube is the main contribution of this work. The decisive design parameters used to optimize the wind cube are its inner and outer radius, the roughness factor, and the height of the wind turbine hub. A Gradient-Based Optimizer (GBO) is used as a new metaheuristic algorithm in this problem. The objective function of this research includes two parts: the first part is to minimize the probability of generated energy loss, and the second is to minimize the cost of the wind turbine and wind cube. The Gradient-Based Optimizer (GBO) is applied to optimize the variables of two wind turbine types and the design of the wind cube. The metrological data of the Red Sea governorate of Egypt is used as a case study for this analysis. Based on the results, the optimum design of a wind cube is achieved, and an improvement in energy produced from the wind turbine with a wind cube will be compared with energy generated without a wind cube. The energy generated from a wind turbine with the optimized cube is more than 20 times that of a wind turbine without a wind cube for all cases studied.