Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition

Natsui, Masanori; Tamakoshi, Akira; Honjo, Haruo; Watanabe, Takahito; Nasuno, T.; Zhang, Chaoliang; Tanigawa, T.; Inoue, Hirofumi; Niwa, Miki; Yoshiduka, T.; Noguchi, Y.; Yasuhira, M.; Ma, Yi; Shen, Hung Tao; Fukami, Shunsuke; Sato, Hideo; Ikeda, Shoji; Ohno, Hideo; Endoh, Tetsuo; Hanyu, Takahiro

doi:10.1109/jssc.2020.3039800

Cited by 35 publications

(10 citation statements)

References 30 publications

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“…For example, the performance of writing-based in-MRAM computing could be enhanced by emerging magnetoelectric RAM (MeRAM) with 5-fJ writing energy and 2-Gb/cm 2 bit density [101][102][103]. A SOT-MRAM with an accessing operational speed of approximately 100 MHz was fabricated in [104], which supports the prospect of a high-speed computing paradigm. Ref.…”

Section: Energy Efficiency Challengementioning

confidence: 82%

A survey of in-spin transfer torque MRAM computing

Cai

Liu

Chen

et al. 2021

Sci. China Inf. Sci.

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In traditional von Neumann computing architectures, the essential transfer of data between the processor and memory hierarchies limits the computational efficiency of next-generation system-on-a-chip. The emerging in-memory computing (IMC) approach addresses this issue and facilitates the movement of significant data and rapid computations. Among the different memory types, intrinsic energy efficiency is demonstrated by in-magnetic random access memory (MRAM) computing with a low-power spintronic magnetic tunnel junction device and hybrid integration at an advanced complementary metal-oxide semiconductor node. This study reviews state-of-the-art techniques for managing IMC with an emphasis on spin-transfer torque-MRAM computing via design schemes at the bit-cell, circuit, and system levels. In addition, this study presents effective design techniques and potential challenges and demonstrates the existing limitations of in-MRAM computing and potential methods for overcoming these issues. This study also considers the design technology co-optimization from the IMC perspective.

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Section: Energy Efficiency Challengementioning

confidence: 82%

A survey of in-spin transfer torque MRAM computing

Cai

Liu

Chen

et al. 2021

Sci. China Inf. Sci.

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“…The endurance figures are different for each technology and depend on the manufacturer and the target market. For instance, STT-RAM endurance is subject to some design parameters tradeoffs such as retention time, area, power efficiency and read/write latency [53,54]. It is therefore not surprising to find in the literature STT-RAM endurance values from 10 6 for embedded systems or IoT applications [53,[55][56][57] up to 10 12 for general purpose microprocessors [18,19,58].…”

Section: Bitcell Endurance Modelmentioning

confidence: 99%

L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime

et al. 2023

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Several emerging non-volatile (NV) memory technologies are rising as interesting alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM memory, are higher density and lower static power, but write operations wear out the bitcells to the point of eventually losing their storage capacity. In this context, this paper presents a novel LLC organization designed to extend the lifetime of the NV data array and a procedure to forecast in detail the capacity and performance of such an NV-LLC over its lifetime. From a methodological point of view, although different approaches are used in the literature to analyze the degradation of an NV-LLC, none of them allows to study in detail its temporal evolution. In this sense, this work proposes a forecasting procedure that combines detailed simulation and prediction, allowing an accurate analysis of the impact of different cache control policies and mechanisms (replacement, wear-leveling, compression, etc.) on the temporal evolution of the indices of interest, such as the effective capacity of the NV-LLC or the system IPC. We also introduce L2C2, a LLC design intended for implementation in NV memory technology that combines fault tolerance, compression, and internal write wear leveling for the first time. Compression is not used to store more blocks and increase the hit rate, but to reduce the write rate and increase the lifetime during which the cache supports near-peak performance. In addition, to support byte loss without performance drop, L2C2 inherently allows N redundant bytes to be added to each cache entry. Thus, L2C2+N, the endurance-scaled version of L2C2, allows balancing the cost of redundant capacity with the benefit of longer lifetime. For instance, as a use case, we have implemented the L2C2 cache with STT-RAM technology. It has affordable hardware overheads compared to that of a baseline NV-LLC without compression in terms of area, latency and energy consumption, and increases up to 6-37 times the time in which 50% of the effective capacity is degraded, depending on the variability in the manufacturing process. Compared to L2C2, L2C2+6 which adds 6 bytes of redundant capacity per entry, that means 9.1% of storage overhead, can increase up to 1.4-4.3 times the time in which the system gets its initial peak performance degraded.

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“…1(a), the SOT-MTJ device has three ports, where W1, W2 are write ports and R is a read port. The write and read paths are separated, which allows the MTJ resistance to be changed to the high level required by IMC by adjusting the tunnel barrier thickness without affecting the write [29], and also avoids the interference of false writes caused by the spin-transfer-torque MTJ (STT-MTJ) when reading data because the read and write operations share a path [30,31]. MTJ has good compatibility with CMOS process, and it can be deposited onto CMOS in the back-end process, as shown in Fig.…”

Section: Sot-mtj Devicementioning

confidence: 99%

A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations

Jin

Yin

Chen

et al. 2023

IEICE Electron. Express

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Traditional von Neumann architecture bottlenecks such as the "memory wall" limit artificial intelligence (AI) development, and inmemory computing (IMC) as a new computing architecture can solve the above problems. Spin-orbit-torque-magnetic random access memory (SOT-MRAM) has very good advantages in IMC architecture because of its good compatibility with CMOS, high tunneling magnetoresistance (TMR) ratio, and high energy efficiency. In this paper, we propose a 6T-3M-based MRAM-IMC architecture with reconfigurable memory mode and logical operation mode. The functionality of the proposed architecture is validated using the 28 nm process design kit and the SOT-MTJ model.

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Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition

Cited by 35 publications

References 30 publications

A survey of in-spin transfer torque MRAM computing

A survey of in-spin transfer torque MRAM computing

L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime

A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations

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