Dual workfunction Ni-silicide/HfSiON gate stacks by phase-controlled full-sificidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices

High-Temperature Stable HfLaON p-MOSFETs With High-Work-Function $\hbox{Ir}_{3}\hbox{Si}$ Gate

“…From the C-V shift to control Al gate on 1000 • C RTAannealed HfLaON, the extracted φ m-eff of Ir 3 Si/HfLaON is 5.08 eV. Here, the Al-gated capacitor was chosen as a reference because low-temperature-deposited pure metal has little 0741-3106/$25.00 © 2007 IEEE Fermi-level pinning on high-κ dielectric [4], [5], [8], [9], and the same 1000 • C RTA ensures the similar oxide charge in HfLaON to Ir 3 Si-gated devices. The Al control gate is used to avoid oxide charge difference on thickness introduced by nitrogen-plasma treatment and process variation.…”

Pre-doping effects on Ni fully silicided metal gate on SiO2 dielectric

“…The NiSi electrode has a mid-gap work function (WF) [6], but threshold voltage (V th ) design requires band edge WFs of gate electrodes (close to conduction band for n-channel metal-oxide-semiconductor (MOS), and close to valence band for p-channel MOS) [6]. Several methods to tune WF were demonstrated such as phase control (NiSi for NMOS, Ni-rich silicide for PMOS), dopant implantation (B, P, As, Sb, Al), and alloying, which allow to reach adequate WF and V th values [4][5][6][7][8][9][10]. This paper investigates Ni FUSI gate process on SiO 2 dielectric, and the predoping effects on the WF of Ni FUSI gate and FUSI gated SiO 2 / Si(1 0 0) interface traps before/after forming gas anneal (FGA).…”

“…Ni-based FUSI metal gate for dual-gate CMOS applications has been investigated extensively due to its excellent compatibility with the conventional CMOS field effect transistor fabrication process [4][5][6][7][8][9][10][11]. The NiSi electrode has a mid-gap work function (WF) [6], but threshold voltage (V th ) design requires band edge WFs of gate electrodes (close to conduction band for n-channel metal-oxide-semiconductor (MOS), and close to valence band for p-channel MOS) [6].…”

Demonstration of short-channel self-aligned Pt/sub 2/Si-FUSI pMOSFETs with low threshold voltage (-0.29 V) on SiON and HfSiON

“…F ULL SILICIDATION (FUSI) of the polysilicon gates in the front-end-of-line processing for integrated circuits is being considered as one of the most promising techniques to integrate the metal gates for the advanced bulk CMOS integration [1]- [4]. However, achieving metal-gate work functions close to the Si conduction-band and valence-band edge for the n-and pMOSFET, respectively, remains a challenge.…”