Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills

Kurokawa, Atsushi; Kanamoto, Toshiki; Ibe, Tetsuya; Kasebe, Akira; Fong, Chang Wei; Kage, Tetsuro; Inoue, Y.; Masuda, H.

doi:10.1109/isqed.2005.47

Cited by 31 publications

(10 citation statements)

References 6 publications

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“…Kahng et al [12] have provided design guidelines to reduce coupling. In [13], Kurokawa et al have provided fill patterns to reduce interconnect coupling. Park et al [14] have presented an exhaustive method to generate capacitance tables for fills.…”

Section: Previous Workmentioning

confidence: 99%

DOE-Based Extraction of CMP, Active and Via Fill Impact on Capacitances

Kahng

Topaloglu

2008

IEEE Trans. Semicond. Manufact.

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Chemical-mechanical polishing (CMP), active and via fills have become indispensable aspects of semiconductor manufacturing. CMP fills are used to reduce metal thickness variations due to chemical-mechanical polishing. Via fills are used to improve neighboring via printability and reliability of low-k and ultra low-k dielectrics. Active region fills are used for STI CMP uniformity and stress optimization. Although modern parasitic extraction tools accurately handle grounded fills and regular interconnects, such tools use only rough approximations to assess the capacitance impact of floating fills, such as assuming that floating fills are grounded or that each fill is merged with neighboring ones. To reduce such inaccuracies, we provide a design of experiments (DOE) which complements what is possible with existing extraction tools. Through the proposed DOE set, a design or mask house can generate normalized fill tables to correct for the inaccuracies of existing extraction tools when floating fills are present. Golden interconnect capacitance values can be updated using these normalized fill tables. Our proposed DOE enables extensive analyses of fill impacts on coupling capacitances. We show through 3-D field solver simulations that the assumptions used in extractors result in significant inaccuracies. We present analyses of fill impacts for an example technology and also provide analyses using the normalized fill tables to be used in the extraction flow for three different standard fill algorithms. We also extend our analyses and methodology to via fills and active region fills, which have more recently been introduced into semiconductor design-manufacturing methodologies and for which sufficient understanding is still lacking.

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Section: Previous Workmentioning

confidence: 99%

DOE-Based Extraction of CMP, Active and Via Fill Impact on Capacitances

Kahng

Topaloglu

2008

IEEE Trans. Semicond. Manufact.

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“…Based on the experimental results, these models are very fast and accurate as compared to current methods built into parasitic extractors. Kurokawa et al [33] propose three techniques of fill insertion in order to reduce the interconnect capacitance and the number of fills inserted. It also provides an estimation of the required number of fill geometries for each of the proposed techniques.…”

Section: B Impact On Rc Parasiticsmentioning

confidence: 99%

Detailed Placement for Enhanced Control of Resist and Etch CDs

Gupta

Kahng

Park³

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We survey recent research and practice in the area of chemical-mechanical polishing (CMP) fill synthesis, in terms of both problem formulations and solution approaches. We review the CMP as the planarization technique of choice for multilevel very large-scale integration metallization processes. Post-CMP wafer topography varies according to pattern density. We review density-analysis methods and density-control objectives that are used in today's fill-synthesis algorithms. In addition, we discuss the concept of design-driven fill synthesis that seeks to optimize CMP fill with respect to objectives beyond mere density uniformity. Design-driven fill synthesis minimizes the impact of CMP fill on design performance and parametric yield while still satisfying the density criteria that are motivated by manufacturing models. We conclude with a discussion of where CMP fill synthesis may be naturally integrated within future design and manufacturing flows.Index Terms-Chemical-mechanical polishing (CMP), CMP fill, design-driven fill, topography.

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“…In particular, these filled features would significantly increase the input data in the following time-consuming reticle enhancement techniques, such as optical proximity correction and phase shift mask. Therefore, much research focuses on impact-limited dummy-feature-filling algorithms [8], [25].…”

Section: Introductionmentioning

confidence: 99%

A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control

Chen

Chou²,

Wang³

et al. 2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-As nanometer technology advances, the post chemical-mechanical polishing (CMP) topography variation control becomes crucial for manufacturing closure. To improve the CMP quality, dummy-feature filling is typically performed by foundries after the routing stage. However, filling dummy features may greatly degrade the interconnect performance and significantly increase the input data in the following timeconsuming reticle enhancement techniques. It is, thus, desirable to consider wire-density uniformity during routing to minimize the side effects from aggressive post-layout dummy filling. In this paper, we present a new full-chip grid-based routing system considering wire density for reticle planarization enhancement. To fully consider a wire distribution, the router applies a novel two-pass top-down planarity-driven routing framework, which employs new density critical area analysis based on Voronoi diagrams and incorporates an intermediate stage of a density-driven layer/track assignment based on incremental Delaunay triangulation. Experimental results show that our methods can achieve a more balanced wire distribution than state-of-the-art works.

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Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills

Cited by 31 publications

References 6 publications

DOE-Based Extraction of CMP, Active and Via Fill Impact on Capacitances

DOE-Based Extraction of CMP, Active and Via Fill Impact on Capacitances

Detailed Placement for Enhanced Control of Resist and Etch CDs

A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control

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