Dummy Oxide Removal in High-K Last Process Integration how to Avoid Silicon Corrosion Issue

Abstract

The industry has diverged into two main approaches for high-k and metal gate (HKMG) integration. One is the so called gate-first. The other is gate-last, also called replacement metal gate (RMG) where the gate electrode is deposited after junctions formation and the high-k gate dielectric is deposited in the beginning of the flow (high-k first-RMG) or just prior to gate electrode deposition (high-k last-RMG) [1-. We can distinguish two RMG process flows called either high-k first or high-k last. In RMG high-k first, poly silicon is removed on top of a TiN etch stop layer whereas on high-k last poly silicon is removed on top of a dummy oxide layer. This dummy oxide has also to be removed in order to redeposit a novel high-k and work function metal (Figure 1).

Effect of Dissolved Oxygen for Advanced Wet Processing

“…Figure 6 shows the SEM images of Si channel trenching after processing by different DO concentrations in dHF. In the dummy oxide removal by dHF, process time control is important to suppress Si channel trenching occurrence caused by over etching [3]. This result shows that the reduction of the DO concentration in dHF can suppress Si channel trenching occurrence and expand the process window.…”

“…Other undesired effects have been reported due to the presence of DO in aqueous solutions in contact with the wafer. During the HF overetch for the dummy gate dielectric removal, enhanced attack of the n+ doped extension regions occurred, leading to shallow trenches being formed adjacent to the spacer [3]. Another issue is the formation of voids in the Ge substrate, at the interface of the spacer and the NiGe region, during the removal of the unreacted Ni using dilute HCl chemistry [4,5].…”

Oxygen Control Challenge for Advanced Wet Processing

“…Figure 5 shows the xs-TEM images of Si channel trenching processing by different DO concentrations in dHF. In processing dummy oxide removal by dHF, process time control is important to suppress Si channel trenching occurrence caused by over etching (3). This result shows that the reduction of DO concentration in dHF can suppress Si channel trenching occurrence in condition of over etching and expand the process window.…”

“…In FEOL processing, other undesired effects have been reported due to the presence of DO in aqueous solutions in contact with the wafer. Firstly it was observed that during the HF overetch for the dummy gate dielectric removal, enhanced attack of the n+ doped extension regions occurred, leading to shallow trenches being formed adjacent to the spacer [3]. Another issue was the formation of voids into the Ge substrate between the spacer and the NiGe region during the removal of the unreacted Ni in case of Ge active regions [4,5].…”