DVFS Aware Techniques on Parallel Architecture Core (PAC) Platform

Tseng, Shau Yin; Chang, Ming Wei

doi:10.1109/icess.symposia.2008.87

Cited by 6 publications

(2 citation statements)

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“…As [8][9][10] [11] state, a processor with lower frequency can have the opportunity to scale operating voltage lower and can get benefit of much lower power. Thereafter, in this paper, when a PACDSP works at 312 MHz, we set its operating voltage to 1.0 volt; when it is at 156 MHz, we adjust the voltage to 0.8 volt.…”

Section: Power Management On Pac Duo Platformmentioning

confidence: 99%

Performance and Power Consumption Analysis of DVFS-Enabled H.264 Decoder on Heterogeneous Multi-Core Platform

Tseng

Lin

Wang

et al. 2010

2010 10th IEEE International Conference on Computer and Information Technology

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Power consumption becomes a very important criterion for the portable embedded devices and, therefore, many Dynamic Voltage/Frequency Scaling (DVFS) techniques have been introduced. This paper is trying to break down and analyze the power consumed by three main components, DSP logic, local memory, and the external DDR2, of a multi-core SoC platform. There are four configurations for this SoC platform: one DSP with full and half clock rates and two DSP's with full and half clock rates. The DSP's in the SoC are clone in the hardware architecture and execute the same H.264/AVC decoder software in all scenarios. With this breakdown, we can figure out the key factors for energy saving and further offer some valuable suggestions for the power management and embedded multi-core SoC designs.

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Section: Power Management On Pac Duo Platformmentioning

confidence: 99%

Performance and Power Consumption Analysis of DVFS-Enabled H.264 Decoder on Heterogeneous Multi-Core Platform

Tseng

Lin

Wang

et al. 2010

2010 10th IEEE International Conference on Computer and Information Technology

Self Cite

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“…The audio/video codec parallelism is exploited from fine-grain 5-way very long instruction word (VLIW) perspective [60]. At the system level the dynamic voltage and frequency scaling scheme is adopted to further reduce the power consumption in PACbased system-on-chip (SoC) for multimedia applications [61]. Processors in this class are often designed with local storage and communication, which are both managed explicitly by software.…”

Section: Visual Computing On Multicore and Reconfigurable Architmentioning

confidence: 99%

Algorithm/Architecture Co-Exploration of Visual Computing on Emergent Platforms: Overview and Future Prospects

Lee

Chen

Mattavelli

et al. 2009

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-Concurrently exploring both algorithmic and architectural optimizations is a new design paradigm. This survey paper addresses the latest research and future perspectives on the simultaneous development of video coding, processing, and computing algorithms with emerging platforms that have multiple cores and reconfigurable architecture. As the algorithms in forthcoming visual systems become increasingly complex, many applications must have different profiles with different levels of performance. Hence, with expectations that the visual experience in the future will become continuously better, it is critical that advanced platforms provide higher performance, better flexibility, and lower power consumption. To achieve these goals, algorithm and architecture co-design is significant for characterizing the algorithmic complexity used to optimize targeted architecture. This paper shows that seamless weaving of the development of previously autonomous visual computing algorithms and multicore or reconfigurable architectures will unavoidably become the leading trend in the future of video technology.

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