Dynamic branch prediction for high-level synthesis

Lapôtre, Vianney; Coussy, Philippe; Wouafo, Hugues Nono; Danilo, Robin

doi:10.1109/fpl.2013.6645540

Cited by 7 publications

(2 citation statements)

References 19 publications

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“…This severely limits the applicability of their work. Gupta et al [8] and Lapotre et al [9] developed techniques to perform control-flow speculationbranch prediction and speculative code motion-in HLS. However, they do not speculate over multiple loop iterations as we do.…”

Section: Effective Throughputmentioning

confidence: 99%

Toward Speculative Loop Pipelining for High-Level Synthesis

Derrien

Marty

Rokicki

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Loop pipelining is a key optimization in modern HLS tools for synthesizing efficient hardware datapaths. Existing techniques for automatic loop pipelining are limited by static analysis that cannot precisely analyze loops with data-dependent control-flow and/or memory accesses. We propose a technique for speculative loop pipelining that handles both control-flow and memory speculations in a unified manner. Our approach is entirely expressed at the source-level, allowing a seamless integration to development flows using HLS. Our evaluation shows significant improvement in throughput over standard loop pipelining.

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Section: Effective Throughputmentioning

confidence: 99%

Toward Speculative Loop Pipelining for High-Level Synthesis

Derrien

Marty

Rokicki

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Much as compilers for VLIW processors do, in order to extract parallelism, many HLS approaches exploit aggressive code motion techniques to anticipate the execution of some operations before it is certain [12,15,17]. However, the conservatism of static scheduling hinders such optimizations in the presence of complex control flow or memory accesses.…”

Section: Related Workmentioning

confidence: 99%

Speculative Dataflow Circuits

Josipović

Guerrieri

Ienne

2019

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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With FPGAs facing broader application domains, the conversion of imperative languages into dataflow circuits has been recently revamped as a way to overcome the conservatism of statically scheduled high-level synthesis. Apart from the ability to extract parallelism in irregular and control-dominated applications, dynamic scheduling opens a door to speculative execution, one of the most powerful ideas in computer architecture. Speculation allows executing certain operations before it is known whether they are correct or required: it can significantly increase fine-grain parallelism in loops where the condition takes many cycles to compute; it can also increase the performance of circuits limited by potential dependencies by assuming independence early on and by reverting to the correct execution if the prediction was wrong. In this work, we detail our methodology to enable tentative and reversible execution in dynamically scheduled dataflow circuits. We create a generic framework for handling speculation in dataflow circuits and show that our approach can achieve significant performance improvements over traditional circuit generation techniques.

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