Dynamic clock stretching for variation compensation in VLSI circuit design

Abstract

In the nanometer era, process, voltage, and temperature variations are dominating circuit performance, power, and yield. Over the past few years, statistical optimization methods have been effective in improving yield in the presence of uncertainty due to process variations. However, statistical methods overconsume resources, even in the absence of variations. Hence, to facilitate a better performance-power-yield trade-off, techniques that can dynamically enable variation compensation are becoming necessary. In this article, we propose a dynamic technique that controls the instance of data capture in critical path memory flops, by delaying the clock edge trigger. The methodology employs a dynamic delay detection circuit to identify the uncertainty in delay due to variations and stretches the clock in the destination flip-flops. The delay detection circuit uses a latch and set of combinational gates to dynamically detect and create the slack needed to accommodate the delay due to variations. The Clock Stretching Logic (CSL) is added only to paths, which have a high probability of failure in the presence of variations. The proposed methodology improves the timing yield of the circuit without significant overcompensation. The methodology approach was simulated using Synopsys design tools for circuit synthesis and Cadence tools for placement and routing of the design. Extraction of parasitic of timing information was parsed using Perl scripts and simulated using a simulation program generated in C++. Experimental results based on Monte-Carlo simulations on benchmark circuits indicate considerable improvement in timing yield with negligible area overhead.

Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations

“…Both random global and local variations were modeled on the threshold voltage of the transistors with a 3σ /μ equal to 21%. Three different SEFF [8]- [10] and three different DCS [12] blocks were added to each critical path along with a normal FF and the two types of DFFC. The three SEFFs and DCSs have different window and skew sizes.…”

“…The three SEFFs and DCSs have different window and skew sizes. The structure of the DCSs is exactly as described in [12], except the TVP block, which is the same as the one used in DFFC. Moreover, as the delay of the minimum paths were so small that no TB was possible, some delay buffers were used to increase them to a proper fraction of the clock period.…”

“…In [11], an algorithm is presented for finding the optimum delay values in a structure called ReCycle. Dynamic clock stretching (DCS) is another structure presented in [12]. It predicts the STVs, and using a multiplexer, it dynamically applies a delayed clock signal to the critical FF.…”

“…In this structure, a timing violation predictor (TVP) detects the STVs halfway in the critical path and, using an XOR gate, converts the FF to a latch so that the late data can still pass the critical FF. The TVP block is an improved version of a circuit presented in [12] and it could have the following two kinds of incorrect predictions.…”

Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention

“…In [10] and [11], the temporal middle point of the critical path is monitored to check if a delay increase to the insertion point causes a transition after half of the clock period. Observe that in the presence of variability effects, the critical path ranking may change.…”