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A machine learning (ML) design framework is proposed for adaptively adjusting clock frequency based on propagation delay of individual instructions. A random forest model is trained to classify propagation delays in real time, utilizing current operation type, current operands, and computation history as ML features. The trained model is implemented in Verilog as an additional pipeline stage within TigerMIPS processor. The modified system is experimentally tested at the gate level in 45 nm CMOS technology, exhibiting simultaneously a speedup of 70% and an energy reduction of 30% with coarse-grained ML classification as compared with the baseline TigerMIPS. A speedup of 89% is demonstrated with finer granularities with a simultaneous 15.5% reduction in energy consumption.

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