Dynamic Communication in a Coarse Grained Reconfigurable Array

Panda, Robin; Hauck, Scott

doi:10.1109/fccm.2011.47

Cited by 6 publications

(2 citation statements)

References 4 publications

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“…This provides very cheap and effective parallelism for streaming computations. Signals between kernels operate with handshaking, moving data independent of the IIs or stalls of the intervening kernels [12]. As such, the inter-kernel wires are more expensive than the intrakernel wires, and thus the length of communication wires between kernels must be carefully controlled.…”

Section: Introductionmentioning

confidence: 99%

Multi-kernel floorplanning for enhanced CGRAS

Wood

Knight

Ylvisaker

et al. 2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

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Signal processing applications have been shown to map well to time multiplexed coarse grained reconfigurable array (CGRA) devices, and can often be decomposed into a set of communicating kernels. This decomposition can facilitate application development and reuse but has significant consequences for tools targeting these devices in terms of allocation and arrangement of resources. This paper presents a CGRA floorplanner to optimize the division and placement of resources for multi-kernel applications. The task is divided into two phases aligned with the respective goals. Resource allocation is accomplished through incremental assignment to minimize performance bottlenecks while operating within the bounds of the maximum available resources. The resulting allocation of resources is arranged in the device using simulated annealing and a perimeter-based cost function which serves to minimize resources needed for both interand intra-kernel communications. The floorplanner is applied to a set of multi-kernel benchmarks demonstrating resource allocations providing maximum throughput across a range of available resources. The algorithms are very fast, taking only a few seconds while producing high quality results. Inter-kernel wire lengths are almost always minimal, and the resource allocation is proven optimal.

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Section: Introductionmentioning

confidence: 99%

Multi-kernel floorplanning for enhanced CGRAS

Wood

Knight

Ylvisaker

et al. 2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

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“…This flexibility has been exploited in SoC IP integration using elastic IP wrappers [2], in hardware units synthesized from dataflow programming models [3], in massively parallel processors [4], [5], as well as in elastic coarse-grained reconfigurable arrays to schedule operations dynamically via elastic control [6].…”

Section: Introductionmentioning

confidence: 99%

Hardware primitives for the synthesis of multithreaded elastic systems

Dimitrakopoulos¹,

Seitanidis²,

Psarras³

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-Elastic systems operate in a dataflow-like mode using a distributed scalable control and tolerating variablelatency computations. At the same time, multithreading increases the utilization of processing units and hides the latency of each operation by time-multiplexing operations of different threads in the datapath. This paper proposes a model to unify multithreading and elasticity. A new multithreaded elastic control protocol is introduced supported by low-cost elastic buffers that minimize the storage requirements without sacrificing performance. To enable the synthesis of multithreaded elastic architectures, new hardware primitives are proposed and utilized in two circuit examples to prove the applicability of the proposed approach.

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