Multi-kernel floorplanning for enhanced CGRAS

Abstract

Signal processing applications have been shown to map well to time multiplexed coarse grained reconfigurable array (CGRA) devices, and can often be decomposed into a set of communicating kernels. This decomposition can facilitate application development and reuse but has significant consequences for tools targeting these devices in terms of allocation and arrangement of resources. This paper presents a CGRA floorplanner to optimize the division and placement of resources for multi-kernel applications. The task is divided into two phases aligned with the respective goals. Resource allocation is accomplished through incremental assignment to minimize performance bottlenecks while operating within the bounds of the maximum available resources. The resulting allocation of resources is arranged in the device using simulated annealing and a perimeter-based cost function which serves to minimize resources needed for both interand intra-kernel communications. The floorplanner is applied to a set of multi-kernel benchmarks demonstrating resource allocations providing maximum throughput across a range of available resources. The algorithms are very fast, taking only a few seconds while producing high quality results. Inter-kernel wire lengths are almost always minimal, and the resource allocation is proven optimal.

Inter‐coarse‐grained reconfigurable architecture reconfiguration technique for efficient pipelining of kernel‐stream on coarse‐grained reconfigurable architecture‐based multi‐core architecture

“…Until now, there have been a few multi‐core architecture projects based on CGRAs [1–16] for kernel‐level parallelism [6, 7–9]. However, most of them are monotonous aggregation of several CGRAs.…”

“…The validation of the proposed approaches is demonstrated through RT-level (RTL) design, synthesis, and simulation of the multi-core architectures with varying the number of CGRAs. Compared with the general multi-CGRAs, the RSFs show area/delay/power overhead of up to 19%/10%/21.73% with increasing the number of CGRAs (4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16). In addition, gate-level simulation of KLP test benches results in performance improvement by up to 88.8% and energy saving by up to 48.2% compared with the conventional architectures.…”

Energy-Efficient and High Performance CGRA-based Multi-Core Architecture

“…Until now, there have been a few multi-core architecture projects based on CGRAs for kernel-level parallelism [2][3][4][5]. However, most of them are monotonous aggregation of several CGRAs.…”