Dynamic coprocessor management for FPGA-enhanced compute platforms

Huang, Chen; Vahid, Frank

doi:10.1145/1450095.1450108

Cited by 20 publications

(14 citation statements)

References 20 publications

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“…In [HV09], the authors continue their work from [HV08], and propose an on-line algorithm that manages coprocessor loading by maintaining an aggregate gain table for all hardware candidates. For each run of a candidate, the performance gain resulted from a hardware execution over a software one is added to the corresponding entry in the table.…”

Section: Dynamic Configuration Prefetchingmentioning

confidence: 99%

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

Lifa¹

2015

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M odern applications running on today's embedded systems have very high requirements. Most often, these requirements have many dimensions: the applications need high performance as well as flexibility, energyefficiency as well as real-time properties, fault tolerance as well as low cost. In order to meet these demands, the industry is adopting architectures that are more and more heterogeneous and that have reconfiguration capabilities. Unfortunately, this adds to the complexity of designing streamlined applications that can leverage the advantages of such architectures.In this context, it is very important to have appropriate tools and design methodologies for the optimization of such systems. This thesis addresses the topic of hardware/software codesign and optimization of adaptive real-time systems implemented on reconfigurable and heterogeneous platforms. We focus on performance enhancement for dynamically reconfigurable FPGA-based systems, energy minimization in multi-mode real-time systems implemented on heterogeneous platforms, and codesign techniques for fault-tolerant systems.The solutions proposed in this thesis have been validated by extensive experiments, ranging from computer simulations to proof of concept implementations on real-life platforms. The results have confirmed the importance of the addressed aspects and the applicability of our techniques for design optimization of modern embedded systems. v vi Populärvetenskaplig Sammanfattning I dag är inbyggda system vanligt förekommande och deras antal fortsätter att öka. De används inom en mängd olika domäner, t.ex. hemelektronik, fordonsindustri, flygelektronik, medicin, etc., och de hittas nästan överallt omkring oss: från våra telefoner, bärbara datorer och tvättmaskiner till våra bilar. De applikationer som körs på dessa system har flera olika ökande krav: högprestanda, energieffektivitet, flexibilitet, feltolerans, realtidsegenskaper, och naturligtvis låg kostnad. För att kunna uppfylla dessa krav har industrin anammat arkitekturer som är mer och mer heterogena och som har omkonfigureringsmöjligheter. Olyckligtvis ökar detta komplexiteten när man ska utforma effektiva inbyggda system. I detta sammanhang blir det av yttersta betydelse att utveckla effektiva optimeringsmetoder och verktyg.Dagens applikationer består av en blandning av mjukvarukomponenter som har mycket olika energi-och prestandaegenskaper beroende på vilka hårdvaruenheter där de körs på, vilket gör dem lämpliga för heterogena plattformar. En heterogen plattform består av olika typer av hårdvaruen-heter, var och en med sina egenskaper, som riktar sig till vissa tillämpn-ingsområden. Under det senaste decenniet har utvecklingen av rekonfigurerbara hårdvarutekniker accelererat, vilket bidrar till den ökande populariteten för fältprogrammerbara grindmatriser (FPGA). Idag, ger hård-varutillverkare stöd för partiell dynamisk omkonfigurering; detta innebär att delar av en FPGA kan konfigureras vid run-time, medan andra delar förblir fullt fungerande. Dessa tekniska framsteg har...

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Section: Dynamic Configuration Prefetchingmentioning

confidence: 99%

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

Lifa¹

2015

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“…For example, if the available area is not sufficient to load the CCU for the current task, CCUs can be swapped if the CB of the current task is higher than that of the to-be-swapped-out set. In [13], this heuristic is used for dynamic coprocessor management of reconfigurable architectures at a low architecture level. The implementation of this heuristic was a little more complicated and resulted with more lines of code than the one of AMAP.…”

Section: Task Mapping Heuristicsmentioning

confidence: 99%

Evaluation of runtime task mapping heuristics with rSesame - a case study

Sigdel¹,

Thompson²,

Galuzzi³

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Abstract-rSesame is a generic modeling and simulation framework which can explore and evaluate reconfigurable systems at the early design stages. The framework can be used to explore different HW/SW partitionings, task mappings and scheduling strategies at both design time and runtime. The framework strives for a high degree of flexibility, ease of use, fast performance and applicability. In this paper, we want to evaluate the framework's characteristics by showing that it can easily and quickly model, simulate and compare a wide range of runtime mapping heuristics from various domains. A case study with a Motion-JPEG (MJPEG) application demonstrates that the presented model can be efficiently used to model and simulate a wide variety of mapping heuristics as well as to perform runtime exploration of various non-functional design parameters such as execution time, number of reconfigurations, area usage, etc.

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“…The authors of [13] present an approach to handle the dynamic loading of coprocessors in order to decrease the execution time of the applications that are currently running on the system. The main limitation of this approach is that only a single coprocessor can be used for each application.…”

Section: Related Workmentioning

confidence: 99%

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems

Rana

Murali

Atienza

et al. 2009

Proceedings of the 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

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Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhanced support for dynamic and partial reconfigurability. Design automation support for partial reconfigurability includes several key challenges. In particular, reconfiguration algorithms need to be developed to effectively exploit the available area and run-time reconfiguration support for instantiating at run-time the hardware components needed to execute multiple applications concurrently. These new algorithms must be able to achieve maximum application execution performance at a minimum reconfiguration overhead.In this work, we propose a novel design flow that minimizes the amount of core reconfigurations needed to map multiple applications dynamically (i.e., using run-time reconfiguration) on FPGAs. This new mapping flow features a multi-stage design optimization algorithm that makes it possible to reduce the reconfiguration latency up to 43%, by taking into account the reconfiguration costs and SoC block reuse between the different applications that need to be executed dynamically on the FPGA. Moreover, we show that the proposed multi-stage optimization algorithm explores a large set of mapping trade-offs, by taking into account the traffic flows for each application, the run-time reconfiguration costs and the number of reconfigurable regions available on the FPGA.

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Dynamic coprocessor management for FPGA-enhanced compute platforms

Cited by 20 publications

References 20 publications

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

Evaluation of runtime task mapping heuristics with rSesame - a case study

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems

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